OperationalStatus 0 (Unknown)
2 (OK), when CPU is enabled and operational
5 (Predictive Failure), when IML error information is
logged for this CPU
6 (Error), when CPU is disabled through POST error
10 (Stopped), when CPU is disabled through RBSU
StatusDescriptions StatusDescriptions[0] text per OperationalStatus[0]:
Unknown
OK
Error
Stopped
HealthState 0 (Unknown), when OperationalStatus[0]=0 (Unknown)
5 (OK), when OperationalStatus[0]=2 (OK)
15 (Minor Failure), when OperationalStatus[0]=10
(Stopped)
20 (Major Failure), when OperationalStatus[0]=5
(Predictive Failure)
25 (Critical Failure), when OperationalStatus[0]=6
(Error)
CIM_LogicalElement
CIM_EnabledLogicalElement
EnabledState 2 (Enabled)
RequestedState 12 (Not Applicable)
EnabledDefault 2 (Enabled)
CIM_HardwareThread
InstanceID HPQ:SMX_HardwareThread: Proc:p Core:c Thread:t
where p is the processor number, c is the core number
and t is the thread number
HP_HardwareThread
SMX_HardwareThread
8-3-5 SMX_CacheMemory
SMX_CacheMemory implements the class HP_CacheMemory which extends CIM_Memory to model
the processor caches.
Table 8-6
Class: SMX_CacheMemory
Property name Property implementation
CIM_ManagedElement
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