Intel® Server Board S2600CW Family TPS Intel® Server Board S2600CW Functional Architecture
Revision 2.4
3.3.6.4 Thermal (CLTT) and Power Throttling
Potential Error Cases:
CLTT Structure Error – The CLTT initialization fails due to an error in the data structure
passed in by the BIOS. This results in a Fatal Error Halt 0xEF.
3.3.6.5 Built-In Self Test (BIST)
Once the memory is functional, a memory test is executed. This is a hardware-based Built In
Self Test (BIST) which confirms minimum acceptable functionality. Any DIMMs which fail are
disabled and removed from the configuration.
Potential Error Cases:
Memory Test Error – The DIMM has failed BIST and is disabled. POST Error Codes 852x
“Failed test/initialization” and 854x “DIMM Disabled” will be generated for each DIMM
that fails. Any DIMMs installed on the channel behind the failed DIMM will be marked
as disabled, with POST Error Code 854x “DIMM Disabled”. This results in a momentary
Error Display 0xEB, and if all DIMMs have failed, this will result in a Fatal Error Halt
0xE8.
No usable memory installed – If no enabled and available memory remains, this will
result in a Fatal Error Halt 0xE8.
The ECC functionality is enabled after all of memory has been cleared to zeroes to make sure
that the data bits and the ECC bits are in agreement.
3.3.6.6 RAS Mode Initialization
If configured, the DIMM configuration is validated for specified RAS mode. If the enabled
DIMM configuration is compliant for the RAS mode selected, then the necessary register
settings are done and the RAS mode is started into operation.
Potential Error Cases:
RAS Configuration Failure – If the DIMM configuration is not valid for the RAS mode
which was selected, then the operating mode falls back to Independent Channel Mode,
and a POST Error Code 8500 “Selected RAS Mode could not be configured” is
generated. In addition, a “RAS Configuration Disabled” SEL entry for “RAS
Configuration Status” (BIOS Sensor 02/Type 0Ch/Generator ID 01) is logged.
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