Intel Stratix 10 Configuration User Guide

Document Version Intel Quartus
Prime Version
Changes
• Moved almost all of the material describing the PFL II flash from an
appendix to the Intel Stratix 10 Configuration Schemes chapter.
• Edited entire document for clarity and style.
• Corrected minor errors and typos.
2018.05.07 18.0 • Removed Estimating the Active Serial Configuration Time section.
•
Updated the OSC_CLK_1 supported frequency.
• Added selecting flash loader step to Generating Programming Files
using Convert Programming Files.
•
Added a note to TCK, TDI, TMS, and TDO stating that they are available
for HPS JTAG chaining in SoC devices.
• Removed instruction to drive nCONFIG low from POR in the following
diagrams:
— Connections for AS x4 Single-Device Configuration
— Connection Setup for AS Configuration with Multiple EPCQ-L Devices
— Connection Setup for Programming the EPCQ-L Devices using the
JTAG Interface
• Added a note in OSC_CLK_1 Clock Input stating that reference clocks
to EMIF and PCIe IP cores must be stable and free running.
• Removed .ekp file from Overview of Intel Quartus Prime Supported
Files and Tools for Configuration and Programming figure.
• Updated the Configuring Intel Stratix 10 Devices using AS
Configuration section title to Generating and Programming AS
Configuration Programming Files.
• Updated Configuration Schemes and Features Overview in Intel Stratix
10 Devices table:
— Added a note stating to contact sales representative for more
information about support readiness.
— Added a note stating to contact sales representative for more
information about flash support other than EPCQ-L devices.
• Removed NAND configuration support.
• Updated Configuration Sequence in Intel Stratix 10 Devices figure by
adding a looped flow arrow during Idle state.
• Updated the MSEL note in Intel Stratix 10 Device Configuration Pins
table.
•
Added a note to recommend OSC_CLK_1 for configuration clock source
in OSC_CLK_1 Clock Input.
• Updated CvP data width and maximum data rate in Configuration
Schemes and Features Overview in Intel Stratix 10 Devices table.
• Removed the multiple EPCQ-L configuration device support.
Date
Version Changes
November 2017 2017.11.09 • Removed link to the Configuration via Protocol (CvP) Implementation
User Guide.
• Updated titles for Device Security, Partial Reconfiguration, and
Configuration via Protocol.
November 2017 2017.11.06 • Updated Option Bits Sector Format table.
• Updated a step in Setting Additional Configuration Pins.
• Added Converting .sof to .pof File and Programming CPLDs and Flash
Memory Devices.
• Updated the .pof version value in Storing Option Bits.
• Added information about restoring start and end address for option
bits in Restoring Option Bit Start and End Address.
•
Added note about pull-down resistor is recommended for CONF_DONE
and INIT_DONE pins in Additional Configuration Pin Functions.
• Added new subsection Multiple EPCQ-L Devices Support.
continued...
8. Document Revision History for the Intel Stratix 10 Configuration User Guide
UG-S10CONFIG | 2018.11.02
Intel Stratix 10 Configuration User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English