Figure 16. Cypress and Micron M28, M29 Flash Memory in 8-Bit Mode
The flash memory addresses in Cypress 8-bit flash shifts one bit up. Address bit 0 of the PFL II IP core
connects to data pin D15 of the flash memory.
23
22
21
-
-
-
2
1
0
PFL II
address: 24 bits
22
21
20
-
-
-
1
0
D15
Flash Memory
address: 24 bits
Figure 17. Cypress and Micron M28, M29 Flash Memory in 16-Bit Mode
The address bit numbers in the PFL II IP core and the flash memory device are the same.
22
21
20
-
-
-
2
1
0
PFL II
address: 23 bits
22
21
20
-
-
-
2
1
0
Flash Memory
address: 23 bits
3.1.6.1.4. Implementing Page in the Flash .pof
The PFL II IP core stores configuration data in a maximum of eight pages in a flash
memory block. Each page holds the configuration data for a single FPGA chain.
The total number of pages and the size of each page depends on the density of the
flash. These pages allow you to store designs for different FPGA chains or different
designs for the same FPGA chain in different pages.
Use the generated .sof files to create a flash memory device .pof. When converting
these .sof files to a .pof, use the following address modes to determine the page
address:
• Block mode—allows you to specify the start and end addresses for the page.
• Start mode—allows you to specify only the start address. You can locate the start
address for each page on an 8-KB boundary. If the first valid start address is
0×000000, the next valid start address is an increment of 0×2000.
• Auto mode—allows the Intel Quartus Prime software to automatically determine
the start address of the page. The Intel Quartus Prime software aligns the pages
on a 128-KB boundary; for example, if the first valid start address is 0×000000,
the next valid start address is an increment of 0×20000.
3. Intel Stratix 10 Configuration Schemes
UG-S10CONFIG | 2018.11.02
Send Feedback
Intel Stratix 10 Configuration User Guide
37
To Next Page
Loading...
Need help?
General
