Intel Stratix 10 Configuration User Guide

You can use the PFL II IP core to either program the flash memory devices, configure
your FPGA, or both. To perform both functions, create separate PFL II functions if any
of the following conditions apply to your design:
• You modify the flash data infrequently.
• You have JTAG or In-System Programming (ISP) access to the configuration host.
• You want to program the flash memory device with non-Intel FPGA data. For
example, the flash memory device contains initialization storage for an ASSP. You
can use the PFL II IP core to program the flash memory device for the following
purposes:
— Write the initialization data
— Create your design source code to implement the read and initialization
control with the host logic
3.1.6.1.3. Mapping PFL II IP Core and Flash Address
The address connections between the PFL II IP core and the flash memory device vary
depending on the flash memory device vendor and data bus width.
Figure 14. Micron J3 Flash Memory in 8-Bit Mode
The address connection between the PFL II IP core and the flash memory device are the same.
23
22
21
-
-
-
2
1
0
PFL II
address: 24 bits
23
22
21
-
-
-
2
1
0
Flash Memory
address: 24 bits
Figure 15. Micron J3, P30, and P33 Flash Memories in 16-Bit Mode
The flash memory addresses in Micron J3, P30, and P33 16-bit flash memory shift one bit down in comparison
with the flash addresses in PFL II IP core. The flash address in the Micron J3, P30, and P33 flash memory starts
from bit 1 instead of bit 0.
22
21
20
-
-
-
2
1
0
PFL II
address: 23 bits
23
22
21
-
-
-
3
2
1
Flash Memory
address: 23 bits
3. Intel Stratix 10 Configuration Schemes
UG-S10CONFIG | 2018.11.02
Intel Stratix 10 Configuration User Guide
Send Feedback
36

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English