Keithley 2002

IEEE-488 Reference
3-12
Figure 3-8
Sequence event status
(B14 - B3)
(B15) (B2)
(B1) (B0)
OR
Sequence
Condition Register
Sequence Event
Enable Register
Lay1 = Layer 1 (Set bit indicates that 2002 is in arm layer 1).
Lay2 = Layer 2 (Set bit indicates that 2002 is in arm layer 2).
& = Logical AND
OR = Logical OR
PTR = Positive Transition Register
NTR = Negative Transition Register
&
&
&
0
Lay2 Lay1
(B14 - B3)
(B15) (B2)
(B1) (B0)
0
Lay2 Lay1
(B14 - B3)
(B15) (B2)
(B1) (B0)
0
Always
Zero
Lay2 Lay1
PTR
NTR
Sequence
Transition Filter
Sequence Event
Register
(B14 - B3)
(B15) (B2) (B1) (B0)
Lay2 Lay1
To Sequence 1 Bit
(Seq 1) of Arm
Event Condition
Register (See
Figure 3-7).