Lust CDA3000 - Page 23

Application Manual CDA3000
2-9
2 Inverter module CDA3000
1
2
3
4
5
6
A
DE
EN
FR
DE
EN
FR
Digital inputs
ISD00 X2-9 • Limit frequency 5 kHz
• PLC-compatible (IEC1131)
• Switching level Low/High: <5 V / >18 V DC
• I
max
at 24 V = 10 mA
• R
IN
= 3 kW
• Internal signal delay time
≈ 100µs
• Terminal scan cycle = 1ms

ISD01 X2-10 • Limit frequency 150 kHz
• PLC-compatible (IEC1131)
• Switching level Low/High: <5 V / >18 V DC
• I
max
at 24 V = 10 mA
• R
IN
= 3 kW
• Internal signal delay time
≈ 2µs
• Terminal scan cycle = 1ms
• Data input with reference coupling (Master/-
Slave)

ISD02 X2-11 • Limit frequency 500 kHz
• PLC-compatible (IEC1131)
• Switching level Low/High: <5 V / >18 V DC
• I
max
at 24 V = 10 mA
• R
IN
= 3 kW
• Internal signal delay time
≈ 2µs
• Terminal scan cycle = 1ms
• A-input with square encoder evaluation for
24V HTL encoder against GND_EXT
• Permissible pulse count 32...16384 pulses
per rev. (2
n
with n = 5...14)

ISD03 X2-12 • Limit frequency 500 kHz
• PLC-compatible (IEC1131)
• Switching level Low/High: <5 V / >18 V DC
• I
max
at 24 V = 10 mA
• R
IN
= 3 kW
• Internal signal delay time
≈ 2µs
• Terminal scan cycle = 1ms
• B-input with square encoder evaluation for
24V HTL encoder against GND_EXT
• Permissible pulse count 32...16384 pulses
per rev. (2
n
with n = 5...14)

Des.
Ter-
minal
Specification Floating
Table 2.6 Specification of control terminals