MEDIATEK Ralink MT7620 - Page 44

PGMT7620_V.1.0_040503
Page 44 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Bits
Type
Name
Description
Initial Value
23
RO
PPLL_LD
PPLL Lock
0: Unlock
1: Lock
-
22:14
RO
EC_PEAFCOUT
PCIe PLL AFC output
0x0
13:10
RO
EC_PEPHDRFT
PCIe PLL Phase Drift
SSCG output code
(two’s complement)
0x0
9:0
RW
FR_PEAFCSET
PCIe PLL AFC Set
0xxxxxxxxx: Normal
1xxxxxxxxx: Manual set
0x0
29. PPLL_DRV: PCIe Driver Configuration (offset: 0x00A0)
Bits
Type
Name
Description
Initial Value
31
RW
PDRV_SW_SET
PCIe Driver Software Set
0: HW sets default parameters
1: SW configures values for [19:0] in this
register.
0x0
30:20
-
-
Reserved
0x0
19
RW
LC_CKDRVPD
(Logic side Code) PCIe Clock Driver Power Down
(Low Active)
0: Power Down
1: Power On
0x0
18
RW
LC_CKDRVOHZ
(Logic side Code) Reference PCIe Output Clock
Mode Enable
0: Enable output clock (Host mode only)
1: High Impedence (Device mode)
0x1
17
RW
LC_CKDRVHZ
(Logic side Code) PCIe PHY Clock Enable
0: Enable clock (Host mode only)
1: High Impedence (Device mode)
0x1
16
RW
LC_CKTEST
(Logic side Code) Single-ended clock for output
testing
0: Normal operation
1: Testing only
0x0
15:0
RW
FR_CKDRVHZ
PCIe Clock Driver Set
(default 0000-0101-0000-0100)
See NOTE below.
0x0504
NOTE: [15:0] bit values are as follows.
Bits
Description
15:13
Reserved
12
Input clock selection
Value
Description
0
From PEPLL
1
From LC_CKTEST