1 MULTIPLE CPU SYSTEM
1.3 Data Communication Between CPU Modules in the Multiple CPU System
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This refresh method is a setting for compatibility with the Q series Motion CPU with the purpose of making the
data refresh timing equivalent to that of "Multiple CPU high speed refresh" of the Q series Motion CPU.
When configuring a new system, we recommend using refresh (I45 executing) for communication of data that
is synchronized with the control of the Motion CPU.
■Operation example of Multiple CPU refresh setting (Q compatibility high-speed refresh
setting)
The operation example of Multiple CPU refresh setting (Q compatibility high-speed refresh setting) is shown below.
Read by main cycle or
operation cycle of
CPU No.2
Write by main
cycle or operation
cycle of CPU No.2
Read by END process
of CPU No.1
CPU No.1
B0 to B1F (CPU No.1)
B20 to B3F (CPU No.2)
Device
Refresh area
CPU buffer memory
Write by END process
of CPU No.1
CPU No.2
B0 to B1F (CPU No.1)
B20 to B3F (CPU No.2)
Device
Refresh area
CPU buffer memory
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