NEC express5800 A2010b - Page 198

1. Installing / Removing Internal Options
Chapter 2 Preparations
(4) Lock Step
In Lock Step mode, pairs of memory channel 0 and 1 or memory channel 2 and 3 are used to perform 128-bit
data access. It supports ECC correction (128-bit Data + 16-Bit ECC) and DDDC (Double Device Data
Correction) that can correct double DRAM errors.
Memory performance is lower than Independent mode (*1), however, RAS feature is higher than Independent
mode.
Note
• Combinations of channels 0 and 1, and 2 and 3 are used in Lock Step mode.
• Use NE3302-H010F/H011F/H012F/H013F additional memory for Lock Step mode.
• Use the DIMMs of same model for Lock Step PAIR.
This feature can be used under the following conditions:
• Both DIMMs in Lock Step Pair (DIMM#1/2, DIMM#3/4, DIMM#5/6, DIMM#7/8) must be of same model.
*1 Performance is measured when DIMM works at the same memory clock speed in Independent mode and
LockStep mode. There is a case that supported clock speed in LockStep mode is higher than in Independent
mode in this server. Confirm the clock speed according to Chapter 2 (1.14.2 Memory Clock).
DIMM #1
DIMM #5
DIMM #2
DIMM #6
CH0
CH1
SMI0
SMI2
SMI3
LockStep
PAIR#1
LockStep
PAIR#3
DIMM #3
DIMM #7
DIMM #4
DIMM #8
CH2
CH3
SMI1
LockStep
PAIR#2
LockStep
PAIR#4
Memory Controller #1
Memory Controller #2
Processor
Memory Buffer #1
Memory Buffer #2
CH0/1 and CH2/3
work as a pair
Memory Riser #1
Express5800/A1040b, A2040b, A2020b, A2010b User's Guide
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