14. Serial I/O
puorG92/C61M
page 181
854fo7002,03.raM21.1.veR
2110-1010B90JER
Table 14.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register Bit Function
UiTB
(3)
0 to 7 Set transmission data
UiRB
(3)
0 to 7 Reception data can be read
OER Overrun error flag
UiBRG 0 to 7 Set bit rate
UiMR
(3)
SMD2 to SMD0 Set to 0012
CKDIR Select the internal clock or external clock
IOPOL(i=2)
(4)
Set to 0
UiC0 CLK1 to CLK0 Select the count source for the UiBRG register
CRS
_______ _______
Select CTS or RTS to use
TXEPT Transmit register empty flag
CRD
_______ _______
Enable or disable the CTS or RTS function
NCH Select TxDi pin output mode
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
UiC1 TE Set this bit to 1 to enable transmission/reception
TI Transmit buffer empty flag
RE Set this bit to 1 to enable reception
RI Reception complete flag
U2IRS
(1)
Select the source of UART2 transmit interrupt
U2RRM
(1)
Set this bit to 1 to use UART2 continuous receive mode
U2LCH
(3)
Set this bit to 1 to use UART2 inverted data logic
U2ERE
(3)
Set to 0
U2SMR 0 to 7 Set to 0
U2SMR2 0 to 7 Set to 0
U2SMR3 0 to 2 Set to 0
NODC Select clock output mode
4 to 7 Set to 0
U2SMR4 0 to 7 Set to 0
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set this bit to 1 to use continuous receive mode
CLKMD0 Select the transfer clock output pin when CLKMD1 is set to 1
CLKMD1 Set this bit to 1 to output UART1 transfer clock from two pins
RCSP
_________
Set this bit to 1 to accept as input the UART0 CTS0 signal from the P64 pin
7 Set to 0
NOTES:
1. Set bits 5 and 4 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the
UCON register.
2. Not all register bits are described above. Set those bits to 0 when writing to the registers in clock
synchronous serial I/O mode.
3. Set bits 7 and 6 in registers U0C1 and U1C1 to 0.
4. Set the bit 7 in registers U0MR and U1MR to 0.
i=0 to 2
To Next Page
Loading...
Need help?
General
