15. A/D Converter
puorG92/C61M
page 250
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 15.26 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (2)
•Example 3: When AD
TRG
input falling edge is generated more than two times after AN
0
pin conversion
AN
0
AN
1
AN
2
AN
3
(invalid)
(valid after single sweep conversion)
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Set to 0 when interrupt request acknowledgement or a program
Set to 0 by program
Do not set to 1 by program
A/D pin input
voltage sampling
A/D pin conversion
ADST flag: Bit 6 in the ADCON0 register
ADERR
ADERR1
ADT
F
AD
TT
AD
TT1
AD
TRT
n
AD
TRT1 fl
:
i
1
4
n
7 in
h
AD
TAT
r
i
r
AD
TRG
pin input