Renesas M16C/29 Series - Page 276

15. A/D Converter
puorG92/C61M
page 250
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 15.26 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (2)
•Example 3: When AD TRG input falling edge is generated more than two times after AN 0 pin conversion
AN 0
AN 1
AN 2
AN 3
(invalid)
(valid after single sweep conversion)
ADST flag
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
IR bit in the ADIC
register
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Set to 0 when interrupt request acknowledgement or a program
Set to 0 by program
Do not set to 1 by program
A/D pin input
voltage sampling
A/D pin conversion
ADST flag: Bit 6 in the ADCON0 register
ADERR
0,
ADERR1
,
ADT
CS
F
,
AD
S
TT
0,
AD
S
TT1
,
AD
S
TRT
0
a
n
d
AD
S
TRT1 fl
ag
:
b
i
ts
0,
1
,
3,
4
,
5,
6
a
n
d
7 in
t
h
e
AD
S
TAT
0
r
eg
i
ste
r
AD
TRG pin input