18. CRC Calculation Circuit
puorG92/C61M
page 314
854fo7002,03.raM21.1.veR
2110-1010B90JER
Figure 18.2. CRCD, CRCIN, CRCMR, CRCSAR Register
Symbol Address After Reset
CRCD 03BD
16 to 03BC16 Undefined
b7 b0 b7 b0
(b15) (b8)
CRC Data Register
Function
Setting Range
0000
16
to FFFF
16
RW
RW
Symbol Address After Reset
CRCIN 03BE
16
Undefined
b7 b0
CRC Input Register
Data input
Function
00
16
to FF
16
RW
RW
Setting Range
CRC calculation result output
Symbol Address After Reset
CRCMR 03B6
16
0XXXXXX02
b7 b0
CRC Mode Register
CRC mode polynomial
selection bit
Function
0: LSB first
1: MSB first
RW
RW
Bit nameBit symbol
CRC mode selection bit
CRCPS
CRCMS
RW
Nothing is assigned.
Write "0" when writing to this bit. The value is indeterminate if read.
0: X
16
+X
12
+X
5
+1 (CRC-CCITT)
1: X
16
+X
15
+X
2
+1 (CRC-16)
CRC mode polynomial
selection bit
Function
0: LSB first
1: MSB first
RW
RW
Bit NameBit Symbol
CRC mode selection bit
CRCPS
CRCMS
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
0: X
16
+X
12
+X
5
+1 (CRC-CCITT)
1: X
16
+X
15
+X
2
+1 (CRC-16)
(b6-b1)
Symbol Address After Reset
CRCSAR 03B5
16 to 03B416 00XXXXXX XXXXXXXX2
b7 b0 b7 b0
(b15) (b8)
SFR Snoop Address Register
CRC mode polynomial
selection bit
Function RW
RW
Bit Name
Bit Symbol
CRCSR
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
SFR address to snoop
Function
0: Disabled
1: Enabled
(1)
RW
CRCSW
CRCSAR9-0
CRC snoop on read
enable bit
CRC snoop on write
enable bit
0: Disabled
1: Enabled
(1)
RW
(b13-b10)
NOTE:
1. Set bits CRCSR and CRCSW to 0 if the PLC07 bit in the PLC0 register is set to 1 (PLL on) and the PM20 bit in
the PM2 register is set to 0 (SFR access 2 wait).
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