1. Overview
page 12
puorG92/C61M
854fo7002,03.raM21.1.veR
2110-1010B90JER
M16C/29 Group (M16C/29)
PLQP0080KB-A
(80P6Q-A)
(top view)
Figure 1.8 Pin Assignment (Top View) of 80-Pin Package
1 2 3 4 5 6 7 8 9 1011121314151617181920
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41424344454647484950515253545557585960
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
56
P6
1
/CLK
0
P35
P34
P33
P32/SOUT3
P31/SIN3
P37
P67/TXD1
P71/RXD2/SCL2/TA0IN/CLK1
P7
2/CLK2/TA1OUT/V/RxD1
P7
3/CTS2/RTS2/TA1IN/V/TxD1
P6
5/CLK1
P66/RxD1
P64/CTS1/RTS1/CTS0/CLKS1
P70/TXD2/SDA2/TA0OUT/CTS1/RTS1/CTS0/CLKS1
P75/TA2IN/W
P3
0/CLK3
P74/TA2OUT/W
P1
0
/AN2
0
P1
1
/AN2
1
P1
2
/AN2
2
P1
5
/INT
3
/AD
TRG
/IDV
P1
6
/INT
4
/IDW
P1
7
/INT
5
/INPC1
7
/IDU
P2
0
/OUTC1
0
/INPC1
0
/SDA
MM
P2
1
/OUTC1
1
/INPC1
1
/SCL
MM
P2
2
/OUTC1
2
/INPC1
2
P2
3
/OUTC1
3
/INPC1
3
P2
4
/OUTC1
4
/INPC1
4
P2
5
/OUTC1
5
/INPC1
5
P2
6
/OUTC1
6
/INPC1
6
P2
7
/OUTC1
7
/INPC1
7
P6
0
/CTS
0
/RTS
0
V
CC
X
IN
X
OUT
V
SS
RESET
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
P76/TA3OUT
P7
7
/TA3
IN
P9
2
/AN3
2
/TB2
IN
/CRX
P9
3
/AN2
4
/CTX
P9
5
/AN2
5
/CLK
4
P9
1
/AN3
1
/TB1
IN
P8
2
/INT
0
P8
3
/INT
1
P8
1
/TA4
IN/U
P8
4
/INT
2
/ZP
P8
0
/TA4
OUT
/U
P8
5
/NMI/SD
P00/AN00
P01/AN01
P02/AN02
P03/AN03
P04/AN04
P05/AN05
P06/AN06
P0
7
/AN0
7
VREF
AVSS
AVcc
P100/AN0
P101/AN1
P102/AN2
P103/AN3
P104/AN4/KI0
P105/AN5/KI1
P106/AN6/KI2
P107/AN7/KI3
P96/AN26/SOUT4
P97/AN27/SIN4
P9
0
/AN3
0
/TB0
IN/CLK
OUT
P63/TXD0
P6
2
/RxD
0
P36
P1
3
/AN2
3
P1
4
NOTE:
1.Set bits PACR2 to PACR0 in the PACR register to "011
2" before
signals are input or output to individual pins after reset. When the
PACR register is not set, signals are not input or output for some
1.4 Pin Assignments
Figures 1.7 and 1.8 show the pin assignments (top view).
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