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22. Usage Notes
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8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot, single-sweep mode, simultaneous sample sweep mode, delayed
trigger mode 0 or delayed trigger mode 1
Check to see that A/D conversion is completed before reading the target ADi register. (Check the
ADIC register’s IR bit to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0
register to 0 (A/D conversion halted), the conversion result of the A/D converter is undefined. The
contents of ADi registers irrelevant to A/D conversion may also become undefined. If while A/D conver-
sion is underway the ADST bit is cleared to 0 in a program, ignore the values of all ADi registers.
10. When setting the ADST bit in the ADCON register to 0 and terminating forcefully by a program in
single sweep conversion mode, A/D delayed trigger mode 0 and A/D delayed trigger mode 1 during
A/D converting operation, the A/D interrupt request may be generated. If this causes a problem, set the
ADST bit to 0 after an interrupt is disabled.
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