Clock-Asynchronous Serial I/O
M30240 Group
Rev.1.00 Sep 24, 2003 Page 219 of 360
Figure 2.68: Operation timing of transmission in UART mode (compliant with SIM interface)
Example of wiring
Example of operation
Microcomputer
SIM card
TxD2
RxD2
Transmit
enable bit (TE)
Transmit buffer
empty flag (Tl)
Transmit buffer
empty flag (Tl)
D0
D1 D2
D3
D4 D5
D6
D7ST
P
Start
bit
Parity
bit
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
“0”
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Transmit
interrupt request
bit (IR)
“0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
D0
D1 D2
D3
D4 D5
D6
D7ST
P
SP
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
Since a parity error occurred, the
“L” level returns from TxD
2
Detects the level
using an interrupt
routine
Detects the level
using an interrupt
routine
D0 D1 D2
D3
D4
D5 D6
D7ST
P
D0 D1 D2
D3
D4
D5 D6
D7ST
P
SP
TXD2 (Note 2)
R
XD2 (Note 2)
Signal line level
(Note 2)
(1) Transmission enabled
(2) Start transmission
(3) Confirm stop bit
(4) Start transmission
(5) Dispose
parity error
Transferred from UART2 transmit buffer register to UART2 transmit register
Data is set in UART2 transmit buffer register
SP
(Note 1)
Note 1: The transmit is started with overflow timing of BRG after writing in a value at the transmit buffer in the timing shown.
Note 2: TxD2 and RxD2 are wire connected as shown in the diagram and should become the same signal but the output signals
become complex so they are shown separately. Also, the signal level resulting from connecting the TxD2 and RxD2 is shown as a
signal line level.
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