Clock-Asynchronous Serial I/O
M30240 Group
Rev.1.00 Sep 24, 2003 Page 220 of 360
Figure 2.69: Set-up procedure of transmission in UART mode (compliant with SIM interface) (1)
Setting UART2 transmit/receive control register 0
UART2 transmit/receive control register 0 [Address 037C 16]
U2C0
Must be fixed to “0” in UART mode
b7 b0
100
BRG count source select bit
0 0 : f
1 is selected
0 1 : f
8 is selected
1 0 : f
32 is selected
1 1 : Inhibited
b1 b0
Valid when bit 4 = “0”
CTS/RTS disable bit
1 : CTS/RTS function enabled
Transmit register empty flag
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register (transmission completed)
Transfer format select bit
Must be “0” (LSB first) in direct format
Continued to the next page
Setting UART2 transmit/receive mode register
UARTi transmit/receive mode register [Address 0378 16]
U2MR
Stop bit length select bit
0 : One stop bit
b7 b0
01010
Odd/even parity select bit (Valid when bit 6 = “1”)
Must be “1” (even parity) in direct format
Parity enable bit
1 : Parity enabled
T
XD, R XD I/O polarity reverse bit
Usually set to “0”
Serial I/O mode select bit
1 0 1 : Transfer data 8 bits long
b2 b1 b0
011
Setting UART2 transmit/receive control register 1
UART2 transmit/receive control register 1 [Address 037D 16]
U2C1
UART2 transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
Error signal output enable bit
1 : Output enabled
b7 b0
0
Invalid in UART mode
Data logic select bit
Must be “0” (no reverse) in direct format
11
Must be fixed to “0” in UART mode