SONIX SN32F264 - Page 7

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version 1.5
8.6.3 SPI n Clock Divider register (SPIn _CLKDIV) (n=0) ............................................................. 93
8.6.4 SPI n Status register (SPIn _STAT) (n=0)................................................................................ 93
8.6.5 SPI n Interrupt Enable register (SPIn _IE) (n=0) .................................................................... 94
8.6.6 SPI n Raw Interrupt Status register (SPIn _RIS) (n=0) ........................................................... 94
8.6.7 SPI n Interrupt Clear register (SPIn _IC) (n=0) ...................................................................... 95
8.6.8 SPI n Data register (SPIn _DATA) (n=0) ................................................................................ 95
8.6.9 SPI n Data Fetch register (SPIn _DF) (n=0) ........................................................................... 95
9
9
9
I2C ............................................................................................................................................................ 96
9.1 OVERVIEW ..................................................................................................................................... 96
9.2 FEATURES ...................................................................................................................................... 96
9.3 PIN DESCRIPTION ......................................................................................................................... 97
9.4 WAVE CHARACTERISTICS ......................................................................................................... 97
9.5 I2C MASTER MODES .................................................................................................................... 98
9.5.1 MASTER TRANSMITTER MODE ............................................................................................ 98
9.5.2 MASTER RECEIVER MODE ................................................................................................... 98
9.5.3 ARBITRATION ......................................................................................................................... 98
9.6 I2C SLAVE MODES ........................................................................................................................ 99
9.6.1 SLAVE TRANSMITTER MODE ............................................................................................... 99
9.6.2 SLAVE RECEIVER MODE ...................................................................................................... 99
9.7 I2C REGISTERS ............................................................................................................................ 100
9.7.1 I2C n Control register (I2Cn_CTRL) (n=0) ........................................................................... 100
9.7.2 I2C n Status register (I2Cn_STAT) (n=0) .............................................................................. 101
9.7.3 I2C n TX Data register (I2Cn_TXDATA) (n=0) .................................................................... 102
9.7.4 I2C n RX Data register (I2Cn_RXDATA) (n=0) .................................................................... 102
9.7.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0) .................................................... 102
9.7.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0) ........................................... 102
9.7.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0) ............................................................ 103
9.7.8 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0) .............................................................. 103
9.7.9 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0) ....................................................... 103
1
1
1
0
0
0
USB FS DEVICE INTERFACE ...................................................................................................... 104
10.1 OVERVIEW ................................................................................................................................... 104
10.2 FEATURES .................................................................................................................................... 104
10.3 PIN DESCRIPTION ....................................................................................................................... 104
10.4 BLOCK DIAGRAM ....................................................................................................................... 105
10.5 USB SRAM ACCESS .................................................................................................................... 105
10.6 USB MACHINE ............................................................................................................................. 106
10.7 USB INTERRUPT .......................................................................................................................... 106
10.8 USB ENUMERATION .................................................................................................................. 107