SONIX SN32F264 - Page 6

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version 1.5
6.7.5 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0) ................................................. 65
6.7.6 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0) .................................................... 66
6.7.7 CT16Bn Match Control register (CT16Bn_MCTRL) (n=1) .................................................... 66
6.7.8 CT16Bn Match Control register 2(CT16Bn_MCTRL2) (n=1) ................................................ 68
6.7.9 CT16Bn Match Control register 3 (CT16Bn_MCTRL3) (n=1) ............................................... 70
6.7.10 CT16Bn Match register 0 (CT16Bn_MR0) (n=0) .................................................................... 71
6.7.11 CT16Bn Match register 0~19, 21~23 (CT16Bn_MR0~19, 21~23) (n=1) ............................... 71
6.7.12 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0) ............................................. 71
6.7.13 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0) ............................................................... 72
6.7.14 CT16Bn External Match register (CT16Bn_EM)(n=1) ........................................................... 72
6.7.15 CT16Bn External Match Control register (CT16Bn_EMC)(n=1) ........................................... 73
6.7.16 CT16Bn External Match Control register 2(CT16Bn_EMC2)(n=1) ....................................... 74
6.7.17 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=1) ................................................ 75
6.7.18 CT16Bn PWM Control register 2 (CT16Bn_PWMCTRL2) (n=1) ........................................... 77
6.7.19 CT16Bn PWM Enable register (CT16Bn_PWMENB) (n=1) ................................................... 78
6.7.20 PWM IO Enable register (CT16Bn_PWMIOENB) (n=1 ) ....................................................... 79
6.7.21 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0, 1) ................................... 81
6.7.22 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,1) ............................................... 82
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WATCHDOG TIMER (WDT) .............................................................................................................. 84
7.1 OVERVIEW ..................................................................................................................................... 84
7.2 BLOCK DIAGRAM ......................................................................................................................... 85
7.3 WDT REGISTERS ........................................................................................................................... 86
7.3.1 Watchdog Configuration register (WDT_CFG) ....................................................................... 86
7.3.2 Watchdog Timer Constant register (WDT_TC)........................................................................ 86
7.3.3 Watchdog Feed register (WDT_FEED) ................................................................................... 87
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SPI ............................................................................................................................................................ 88
8.1 OVERVIEW ..................................................................................................................................... 88
8.2 FEATURES ...................................................................................................................................... 88
8.3 PIN DESCRIPTION ......................................................................................................................... 88
8.4 INTERFACE DESCRIPTION ......................................................................................................... 89
8.4.1 SPI ............................................................................................................................................ 89
8.4.2 COMMUNICATION FLOW ..................................................................................................... 90
8.4.2.1 SINGLE-FRAME ................................................................................................................. 90
8.4.2.2 MULTI-FRAME .................................................................................................................. 91
8.5 AUTO-SEL ....................................................................................................................................... 91
8.6 SPI REGISTERS .............................................................................................................................. 92
8.6.1 SPI n Control register 0 (SPIn_CTRL0) (n=0) ........................................................................ 92
8.6.2 SPI n Control register 1 (SPIn_CTRL1) (n=0) ........................................................................ 93