ST STM32F0 Series User Manual

About this document PM0215
10/91 Doc ID 022979 Rev 1
1.3.1 System level interface
The Cortex-M0 processor provides a single system-level interface using AMBA
®
technology
to provide high speed, low latency memory accesses.
1.3.2 Integrated configurable debug
The Cortex-M0 processor implements a complete hardware debug solution, with extensive
hardware breakpoint and watchpoint options. This provides high system visibility of the
processor, memory and peripherals through a 2-pin Serial Wire Debug (SWD) port that is
ideal for small package devices.
1.3.3 Cortex-M0 processor features and benefits summary
● High code density with 32-bit performance
● Tools and binary upwards compatible with Cortex-M processor family
● Integrated ultra low-power sleep modes
● Efficient code execution permits slower processor clock or increases sleep mode time
● Single-cycle 32-bit hardware multiplier
● Zero jitter interrupt handling
● Extensive debug capabilities
1.3.4 Cortex-M0 core peripherals
The peripherals are:
● Nested vectored interrupt controller: The NVIC is an embedded interrupt controller that
supports low latency interrupt processing.
● System control block: The SCB is the programmers model interface to the processor. It
provides system implementation information and system control, including
configuration, control, and reporting of system exceptions.
● System timer: SysTick is a 24-bit count-down timer. Use this as a Real Time Operating
System (RTOS) tick timer or as a simple counter.

ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history