The STM32 Cortex-M0 instruction set PM0215
36/91 Doc ID 022979 Rev 1
3.3 About the instruction descriptions
The following sections give more information about using the instructions:
● Operands on page 36
● Restrictions when using PC or SP on page 36
● Shift operations on page 36
● Address alignment on page 39
● PC-relative expressions on page 39
● Conditional execution on page 39
3.3.1 Operands
An instruction operand can be:
● an ARM register,
● a constant,
● or another instruction-specific parameter.
Instructions act on the operands and often store the result in a destination register.
When there is a destination register in the instruction, it is usually specified before the
operands. Operands in some instructions are flexible in that they can either be a register or
a constant (see Shift operations).
3.3.2 Restrictions when using PC or SP
Many instructions have restrictions on whether you can use the program counter (PC) or
stack pointer (SP) for the operands or destination register. See instruction descriptions for
more information.
Bit[0] of any address written to the PC with a BX, BLX or POP instruction must be 1 for
correct execution, because this bit indicates the required instruction set, and the Cortex-M0
processor only supports thumb instructions. When a BL or BLX instruction writes the value
of bit[0] into the LR it is automatically assigned the value 1.
3.3.3 Shift operations
Register shift operations move the bits in a register left or right by a specified number of bits,
the shift length. Register shift can be performed directly by the instructions ASR, LSR, LSL
and ROR. The result is written to a destination register.
The permitted shift lengths depend on the shift type and the instruction (see the individual
instruction description).
● If the shift length is 0, no shift occurs.
● Register shift operations update the carry flag except when the shift length is 0.
The following sub-sections describe the various shift operations and how they affect the
carry flag. In these descriptions,
Rm
is the register containing the value to be shifted, and
n
is
the shift length.
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