ST STM32F0 Series User Manual

PM0215 The STM32 Cortex-M0 instruction set
Doc ID 022979 Rev 1 37/91
ASR
Arithmetic shift right by n bits moves the left-hand 32 - n bits of the register Rm , to the right by
n places, into the right-hand 32 - n bits of the result. And it copies the original bit[31] of the
register into the left-hand
n bits of the result (see Figure 10: ASR#3).
You can use the
ASR operation to divide the signed value in the register Rm by 2
n
, with the
result being rounded towards negative-infinity.
When the instruction is ASRS, the carry flag is updated to the last bit shifted out, bit[
n -1], of
the register
Rm .
Note: 1 If
n is 32 or more, all the bits in the result are set to the value of bit[31] of Rm .
2If
n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm .
Figure 10. ASR#3
LSR
Logical shift right by n bits moves the left-hand 32 - n bits of the register Rm , to the right by n
places, into the right-hand
32 - n bits of the result. And it sets the left-hand n bits of the result
to 0 (see Figure 11).
You can use the LSR #n operation to divide the value in the register
Rm by 2
n
, if the value is
regarded as an unsigned integer.
When the instruction is LSRS, the carry flag is updated to the last bit shifted out, bit[
n -1], of
the register
Rm .
Note: 1 If n is 32 or more, then all the bits in the result are cleared to 0.
2If
n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 11. LSR#3
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ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history