The STM32 Cortex-M0 processor PM0215
12/91 Doc ID 022979 Rev 1
2.1.3 Core registers
Figure 2. Processor core registers
General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
Table 3. Core register set summary
Name Type
(1)
1. Describes access type during program execution in Thread and Handler modes. Debug access can differ.
Reset value Description
R0-R12 read-write Unknown General-purpose registers on page 12
MSP read-write See description Stack pointer (SP) register R13 on page 13
PSP read-write Unknown Stack pointer (SP) register R13 on page 13
LR read-write Unknown Link register (LR) register R14 on page 13
PC read-write See description Program counter (PC) register R15 on page 13
PSR read-write Unknown
(2)
2. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.
Program status register on page 13
ASPR read-write Unknown Application program status register on page 14
IPSR read-only 0x00000000 Interrupt program status register on page 14
EPSR read-only Unknown
(2)
Execution program status register on page 15
PRIMASK read-write 0x00000000 Priority mask register on page 15
CONTROL read-write 0x00000000 Control register on page 16
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