ST STM32F0 Series User Manual

PM0215 The STM32 Cortex-M0 instruction set
Doc ID 022979 Rev 1 67/91
3.7.10 SVC
Supervisor call.
Syntax
SVC #imm
where: ‘imm’ is an integer in the range 0-255.
Operation
The SVC instruction causes the SVC exception. imm is ignored by the processor. It can be
retrieved by the exception handler to determine what service is being requested.
Restrictions: None
Condition flags
This instruction does not change the flags.
Examples
SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
3.7.11 WFE
Wait for event. WFE is a hint instruction.
Syntax
WFE
Operation
If the event register is 0, WFE suspends execution until one of the following events occurs:
● An exception, unless masked by exception mask registers or the current priority level
● An exception enters Pending state, if SEVONPEND in system control register is set
● A Debug Entry request, if Debug is enabled
● An event signaled by a peripheral or another processor in a multiprocessor system
using the SEV instruction.
If the event register is 1, WFE clears it to 0 and returns immediately. For more information
see Power management on page 28.
WFE is intended for power saving only. When writing software assume that WFE might
behave as NOP.
Restrictions: None
Condition flags
This instruction does not change the flags.
Examples
WFE ; Wait for event

ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history