ST STM32F0 Series - 2.2 Memory model

The STM32 Cortex-M0 processor PM0215
18/91 Doc ID 022979 Rev 1
2.2 Memory model
This section describes the processor memory map, and the behavior of memory accesses.
The processor has a fixed memory map that provides up to 4 GB of addressable memory.
Figure 6. Memory map
The processor reserves regions of the Private peripheral bus (PPB) address range for core
peripheral registers, see Section 4.1: About the STM32 Cortex-M0 core peripherals on
page 69.
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