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The STM32 Cortex-M0 processor PM0215

18/91 Doc ID 022979 Rev 1

2.2 Memory model

This section describes the processor memory map, and the behavior of memory accesses.

The processor has a fixed memory map that provides up to 4 GB of addressable memory.

Figure 6. Memory map

The processor reserves regions of the Private peripheral bus (PPB) address range for core

peripheral registers, see Section 4.1: About the STM32 Cortex-M0 core peripherals on

page 69.

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Table 1. Applicable Products1
Table of Contents2
About this Document8
Typographical Conventions8
List of Abbreviations for Registers8
About the STM32 Cortex-M0 Processor and Core Peripherals9
Figure 1. STM32 Cortex-M0 Implementation9
System Level Interface10
Integrated Configurable Debug10
Cortex-M0 Processor Features and Benefits Summary10
Cortex-M0 Core Peripherals10
The STM32 Cortex-M0 Processor11
Programmers Model11
Processor Modes11
Stacks11
Table 2. Summary of Processor Mode and Stack Usage11
Core Registers12
Table 3. Core Register Set Summary12
Figure 2. Processor Core Registers12
Table 4. PSR Register Combinations and Attributes13
Figure 3. APSR, IPSR and EPSR Bit Assignments13
Table 5. APSR Bit Definitions14
Table 6. IPSR Bit Definitions14
Table 7. EPSR Bit Definitions15
Figure 4. PRIMASK Register Bit Assignments15
Table 8. PRIMASK Register Bit Definitions16
Table 9. CONTROL Register Bit Definitions16
Figure 5. CONTROL Register Bit Assignments16
Exceptions and Interrupts17
Data Types17
The Cortex Microcontroller Software Interface Standard (CMSIS)17
Memory Model18
Figure 6. Memory Map18
Memory Regions, Types and Attributes19
Memory System Ordering of Memory Accesses19
Table 10. Ordering of Memory Accesses19
Behavior of Memory Accesses20
Software Ordering of Memory Accesses20
Table 11. Memory Access Behavior20
Memory Endianness21
Figure 7. Little-Endian Example21
Exception Model22
Exception States22
Exception Types22
Exception Handlers23
Table 12. Properties of the Different Exception Types23
Vector Table24
Figure 8. Vector Table24
Exception Priorities25
Exception Entry and Return25
Figure 9. Cortex-M0 Stack Frame Layout26
Table 13. Exception Return Behavior27
Fault Handling28
Power Management28
Entering Sleep Mode29
Wakeup from Sleep Mode29
The External Event Input30
Power Management Programming Hints30
The STM32 Cortex-M0 Instruction Set31
Instruction Set Summary31
Table 14. Cortex-M0 Instructions31
CMSIS Intrinsic Functions35
Table 15. CMSIS Intrinsic Functions to Generate some Cortex-M0 Instructions35
Table 16. CMSIS Intrinsic Functions to Access the Special Registers35
About the Instruction Descriptions36
Operands36
Restrictions When Using PC or SP36
Shift Operations36
Figure 10. ASR#337
Figure 11. LSR#337
Figure 12. LSL#338
Figure 13. ROR #338
Address Alignment39
PC-Relative Expressions39
Conditional Execution39
Table 17. Condition Code Suffixes and Their Relationship with the Flags40
Memory Access Instructions41
Table 18. Memory Access Instructions41
Adr42
LDR and STR, Immediate Offset43
LDR and STR, Register Offset44
LDR, PC-Relative45
LDM and STM46
PUSH and POP47
General Data Processing Instructions48
Table 19. Data Processing Instructions48
ADD{S}, ADCS, SUB{S}, SBCS, and RSBS49
Table 20. ADCS, ADD, RSBS, SBCS and SUB Operand Restrictions50
ANDS, ORRS, EORS and BICS51
ASRS, LSLS, LSRS and RORS52
CMP and CMN53
MOV, MOVS and MVNS54
Muls55
REV, REV16, and REVSH56
SXTB, SXTH, UXTB and UXTH57
Tst58
Branch and Control Instructions59
B, BL, BX, and BLX59
Table 21. Branch and Control Instructions59
Table 22. Branch Ranges59
Miscellaneous Instructions61
Bkpt61
Table 23. Miscellaneous Instructions61
Cpsid Cpsie62
Dmb63
Dsb63
Isb64
Mrs64
Msr65
Nop66
Sev66
Svc67
Wfe67
Wfi68
Core Peripherals69
About the STM32 Cortex-M0 Core Peripherals69
Table 24. STM32 Core Peripheral Register Regions69
Nested Vectored Interrupt Controller (NVIC)70
Accessing the Cortex-M0 NVIC Registers Using CMSIS70
Table 25. NVIC Register Summary70
Table 26. CMSIS Access NVIC Functions70
Interrupt Set-Enable Register (ISER)71
Interrupt Clear-Enable Register (ICER)71
Interrupt Set-Pending Register (ISPR)72
Interrupt Clear-Pending Register (ICPR)72
Interrupt Priority Register (IPR0-IPR7)73
Table 27. IPR Bit Assignments73
Figure 14. IPR Register Mapping73
Level-Sensitive and Pulse Interrupts74
NVIC Design Hints and Tips75
Table 28. CMSIS Functions for NVIC Control75
NVIC Register Map76
Table 29. NVIC Register Map and Reset Values76
System Control Block (SCB)77
CPUID Base Register (CPUID)77
Table 30. Summary of the System Control Block Registers77
Interrupt Control and State Register (ICSR)78
Application Interrupt and Reset Control Register (AIRCR)80
System Control Register (SCR)81
Configuration and Control Register (CCR)82
System Handler Priority Registers (Shprx)83
Table 31. System Fault Handler Priority Fields and Registers83
SCB Usage Hints and Tips84
SCB Register Map84
Table 32. SCB Register Map and Reset Values84
Systick Timer (STK)85
Table 33. System Timer Registers Summary85
Systick Control and Status Register (STK_CSR)86
Systick Reload Value Register (STK_RVR)87
Systick Current Value Register (STK_CVR)87
Systick Calibration Value Register (STK_CALIB)88
Table 34. Systick Register Map and Reset Values89
Table 35. Document Revision History90

Brand	ST
Model	STM32F0 Series
Category	Microcontrollers
Language	English

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