ST STM32F0 Series User Manual

The STM32 Cortex-M0 instruction set PM0215
38/91 Doc ID 022979 Rev 1
LSL
Logical shift left by n bits moves the right-hand 32 - n bits of the register Rm , to the left by n
places, into the left-hand
32 - n bits of the result. And it sets the right-hand n bits of the result
to 0 (see Figure 12: LSL#3 on page 38).
You can use the LSL #n operation to multiply the value in the register
Rm by 2
n
, if the value
is regarded as an unsigned integer or a two’s complement signed integer. Overflow can
occur without warning.
When the instruction is
LSLS or when LSL #n , with non-zero n , is used in operand2 with the
instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag
is updated to the last bit shifted out, bit[
32 - n ], of the register Rm . These instructions do not
affect the carry flag when used with LSL #0.
Note: 1 If
n is 32 or more, then all the bits in the result are cleared to 0.
2If
n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 12. LSL#3
ROR
Rotate right by n bits moves the left-hand 32 - n bits of the register Rm , to the right by n places,
into the right-hand
32 - n bits of the result. It also moves the right-hand n bits of the register
into the left-hand
n bits of the result (see Figure 13).
When the instruction is RORS, the carry flag is updated to the last bit rotation, bit[
n -1], of the
register
Rm .
Note: 1 If
n is 32, then the value of the result is same as the value in Rm , and if the carry flag is
updated, it is updated to bit[31] of
Rm .
2
ROR with shift length, n , more than 32 is the same as ROR with shift length n -32.
Figure 13. ROR #3
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ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history