ST STM32F0 Series User Manual

PM0215 The STM32 Cortex-M0 processor
Doc ID 022979 Rev 1 11/91
2 The STM32 Cortex-M0 processor
2.1 Programmers model
This section describes the Cortex-M0 programmers model. In addition to the individual core
register descriptions, it contains information about the processor modes and stacks.
2.1.1 Processor modes
The processor modes are:
The Cortex-M0 does not support multiple privilege levels. It can always use all instructions
and access all resources.
2.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer indicates the last
stacked item on the stack memory. When the processor pushes a new item onto the stack, it
decrements the stack pointer and then writes the item to the new memory location.
The processor implements two stacks, with independent copies of the stack pointer,( see
Stack pointer (SP) register R13 on page 13):
● the main stack and
● the process stack,
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see Control register on page 16.
In Handler mode, the processor always uses the main stack.
The options for processor operations are:
Thread mode: Used to execute application software.
The processor enters Thread mode when it comes out of reset.
Handler mode: Used to handle exceptions.
The processor returns to Thread mode when it has finished exception
processing.
Table 2. Summary of processor mode and stack usage
Processor mode Used to execute Stack used
Thread Applications Main stack or process stack
(1)
1. See Control register on page 16.
Handler Exception handlers Main stack

ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history