PM0215 The STM32 Cortex-M0 processor
Doc ID 022979 Rev 1 11/91
2 The STM32 Cortex-M0 processor
2.1 Programmers model
This section describes the Cortex-M0 programmers model. In addition to the individual core
register descriptions, it contains information about the processor modes and stacks.
2.1.1 Processor modes
The processor modes are:
The Cortex-M0 does not support multiple privilege levels. It can always use all instructions
and access all resources.
2.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer indicates the last
stacked item on the stack memory. When the processor pushes a new item onto the stack, it
decrements the stack pointer and then writes the item to the new memory location.
The processor implements two stacks, with independent copies of the stack pointer,( see
Stack pointer (SP) register R13 on page 13):
● the main stack and
● the process stack,
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see Control register on page 16.
In Handler mode, the processor always uses the main stack.
The options for processor operations are:
Thread mode: Used to execute application software.
The processor enters Thread mode when it comes out of reset.
Handler mode: Used to handle exceptions.
The processor returns to Thread mode when it has finished exception
processing.
Table 2. Summary of processor mode and stack usage
Processor mode Used to execute Stack used
Thread Applications Main stack or process stack
(1)
1. See Control register on page 16.
Handler Exception handlers Main stack
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