ST STM32F0 Series User Manual

PM0215 Core peripherals
Doc ID 022979 Rev 1 83/91
4.3.6 System handler priority registers (SHPRx)
The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the exception handlers that
have configurable priority. SHPR2-SHPR3 are word accessible. To access the system
exception priority level using CMSIS, use the following CMSIS functions (where the input
parameter IRQn is the IRQ number):
● uint32_t NVIC_GetPriority(IRQn_Type IRQn)
● void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Each PRI_n field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
System handler priority register 2 (SHPR2)
Address offset: 0x1C
Reset value: 0x0000 0000
System handler priority register 3 (SHPR3)
Address: 0xE000 ED20
Reset value: 0x0000 0000
Table 31. System fault handler priority fields and registers
Handler Field Register description
SVCall PRI_11 System handler priority register 2 (SHPR2) on page 83
PendSV PRI_14
System handler priority register 3 (SHPR3) on page 83
SysTick PRI_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
Reserved
rw rw rw rw r r r r
1514131211109876543210
Reserved
Bits 31:24 PRI_11: Priority of system handler 11, SVCall
Bits 23:0 Reserved, must be kept cleared
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15 PRI_14
rw rw rw rw r r r r rw rw rw rw r r r r
1514131211109876543210
Reserved
Bits 31:24 PRI_15: Priority of system handler 15, SysTick exception.
This is Reserved when the SysTick timer is not implemented.
Bits 23:16 PRI_14: Priority of system handler 14, PendSV
Bits 15:0 Reserved, must be kept cleared

ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history