The STM32 Cortex-M0 processor PM0215
28/91 Doc ID 022979 Rev 1
2.4 Fault handling
Faults are a subset of the exceptions, see Exception model on page 22. All faults result in
the HardFault exception being taken or cause lockup if they occur in the NMI or HardFault
handler. The faults are:
● execution of an SVC instruction at a priority equal or higher than SVCall
● execution of a BKPT instruction without a debugger attached
● a system-generated bus error on a load or store
● execution of an instruction from an XN memory address
● execution of an instruction from a location for which the system generates a bus fault
● a system-generated bus error on a vector fetch
● execution of an Undefined instruction
● execution of an instruction when not in Thumb-State as a result of T-bit being previously
cleared to 0
● an attempted load or store to an unaligned address.
Note: Only Reset and NMI can preempt the fixed priority HardFault handler. A HardFault can
preempt any exception other than Reset, NMI, or another hard fault.
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard
fault handlers, or if the system generates a bus error when unstacking the PSR on an
exception return using the MSP. When the processor is in lockup state it does not execute
any instructions. The processor remains in lockup state until either:
● It is reset
● An NMI occurs and the current lockup is in the HardFault handler.
● It is halted by a debugger.
If lockup state occurs from the NMI handler a subsequent NMI does not cause the processor
to leave lockup state.
2.5 Power management
The STM32 and Cortex-M0 processor sleep modes reduce power consumption:
● Sleep mode stops the processor clock. All other system and peripheral clocks may still
be running.
● Deep sleep mode stops most of the STM32 system and peripheral clocks. At product
level, this corresponds to either the Stop or the Standby mode. For more details, please
refer to the “Power modes” Section in the STM32 reference manual.
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see System control
register (SCR) on page 81. For more information about the behavior of the sleep modes see
the STM32 product reference manual.
This section describes the mechanisms for entering sleep mode, and the conditions for
waking up from sleep mode.
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