PM0215 The STM32 Cortex-M0 instruction set
Doc ID 022979 Rev 1 49/91
3.5.1 ADD{S}, ADCS, SUB{S}, SBCS, and RSBS
Add, add with carry, subtract, subtract with carry, and reverse subtract.
Syntax
ADCS {Rd,} Rn, Rm
ADD{S} {Rd,} Rn, <Rm|#imm>
RSBS {Rd,} Rn, Rm, #0
SBCS {Rd,} Rn, Rm
SUB{S} {Rd,} Rn, <Rm|#imm>
where:
● S: causes an ADD or SUB instruction to update flags
● Rd: specifies the result register. If omitted,this value is assumed to take the same value
as Rn, for example ADDS R1,R2 is identical to ADDS R1,R1,R2.
● Rn: specifies the first source register
● Rm: specifies the second source register
● imm: specifies a constant immediate value.
Operation
The ADCS instruction adds the value in Rn to the value in Rm, adding a further one if the
carry flag is set, places the result in the register specified by Rd and updates the N, Z, C,
and V flags.
The ADD instruction adds the value in Rn to the value in Rm or an immediate value
specified by imm and places the result in the register specified by Rd.
The ADDS instruction performs the same operation as ADD and also updates the N, Z, C
and V flags.
The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic negative
of the value, and places the result in the register specified by Rd and updates the N, Z, C
and V flags.
The SBCS instruction subtracts the value of Rm from the value in Rn, deducts a further one
if the carry flag is set. It places the result in the register specified by Rd and updates the N,
Z, C and V flags.
The SUB instruction subtracts the value in Rm or the immediate specified by imm. It places
the result in the register specified by Rd.
The SUBS instruction performs the same operation as SUB and also updates the N, Z, C
and V flags.
Use ADC and SBC to synthesize multiword arithmetic (see Multiword arithmetic examples
on page 50 and ADR on page 42).
Restrictions
Tabl e 20 lists the legal combinations of register specifiers and immediate values that can be
used with each instruction.
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