The STM32 Cortex-M0 instruction set PM0215
52/91 Doc ID 022979 Rev 1
3.5.3 ASRS, LSLS, LSRS and RORS
Arithmetic shift right, logical shift left, logical shift right, and rotate right.
Syntax
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
where:
● ‘Rd’ is the destination register. If Rd is omitted, it is assumed to take the same value as
Rm.
● ‘Rm’ is the register holding the value to be shifted
● ‘Rs’ is the register holding the shift length to apply to the value Rm.
● ‘imm’ is the shift length. The range of shift lengths depend on the instruction as follows:
ASR: Shift length from 1 to 32
LSL: Shift length from 0 to 31
LSR: Shift length from 1 to 32
Note: MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left, logical-shift-right
or a right-rotation of the bits in the register Rm by the number of places specified by the
immediate imm or the value in the least-significant byte of the register specified by Rs.
For details on what result is generated by the different instructions (see Shift operations on
page 36).
Restrictions
In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate
instructions, Rd and Rm must specify the same register..
Condition flags
These instructions:
● Update the N and Z flags according to the result
● The C flag is updated to the last bit shifted out, except when the shift length is 0 (see
Shift operations on page 36).
Examples
ASRS R7, R5, #9 ; Arithmetic shift right by 9 bits
LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSRS R4, R5, #6 ; Logical shift right by 6 bits
RORS R4, R4, R6 ; Rotate right by the value in the bottom byte of R6.
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