ST STM32F0 Series User Manual

The STM32 Cortex-M0 instruction set PM0215
46/91 Doc ID 022979 Rev 1
3.4.5 LDM and STM
Load and store multiple registers.
Syntax
LDM Rn{!}, reglist
STM Rn!, reglist
where:
● ‘Rn’ is the register on which the memory addresses are based
● ‘!’ is an optional writeback suffix. If ! is present, the final address that is loaded from or
stored to is written back into Rn.
● ‘reglist’ is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma-separated if it contains more than one
register or register range (see Examples on page 46).
LDMIA and LDMFD are synonyms for LDM. LDMIA refers to the base register being
Incremented After each access. LDMFD refers to its use for popping data from Full
Descending stacks.
STMIA and STMEA are synonyms for STM. STMIA refers to the base register being
Incremented After each access. STMEA refers to its use for pushing data onto Empty
Ascending stacks.
Operation
LDM loads the registers in reglist with word values from memory addresses based on Rn.
STM stores the word values in the registers in
reglist to memory addresses based on Rn.
The memory addresses used for accesses are at 4-byte intervals ranging from Rn to Rn + 4
* (
n -1), where n is the number of registers in reglist. The accesses happen in order of
increasing register numbers, with the lowest numbered register using the lowest memory
address and the highest number register using the highest memory address. If the
writeback suffix is specified, the value in the register specified by of Rn + 4 * (
n ) or is written
back to the register specified by Rn.
Restrictions
In these instructions:
● reglist and Rn are limited to R0-R7.
● the writeback suffix must always be used unless the instruction is an LDM where reglist
also contains Rn, in which case the writeback suffix must not be used.
● the value in the register specified by Rn must be word aligned. See Address alignment
on page 39 for more information.
● for STM, if Rn appears in reglist, then it must be the first register in the list.
Condition flags
These instructions do not change the flags.
Examples
LDM R0,{R0,R3,R4} ; LDMIA is a synonym for LDM
STMIA R1!,{R2-R4,R6}

ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history