ST STM32F0 Series User Manual (English)

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PM0215 The STM32 Cortex-M0 processor

Doc ID 022979 Rev 1 25/91

2.3.5 Exception priorities

As Table 12 on page 23 shows, all exceptions have an associated priority, with:

● A lower priority value indicating a higher priority

● Configurable priorities for all exceptions except Reset, Hard fault, and NMI.

If software does not configure any priorities, then all exceptions with a configurable priority

have a priority of 0. For information about configuring exception priorities see:

● System handler priority registers (SHPRx) on page 83

● Interrupt priority register (IPR0-IPR7) on page 73

Configurable priority values are in the range 0-192, in steps of 64. This means that the

Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have

higher priority than any other exception.

For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1]

means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted,

IRQ[1] is processed before IRQ[0].

If multiple pending exceptions have the same priority, the pending exception with the lowest

exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending

and have the same priority, then IRQ[0] is processed before IRQ[1].

When the processor is executing an exception handler, the exception handler is preempted

if a higher priority exception occurs. If an exception occurs with the same priority as the

exception being handled, the handler is not preempted, irrespective of the exception

number. However, the status of the new interrupt changes to pending.

2.3.6 Exception entry and return

Descriptions of exception handling use the following terms:

Preemption When the processor is executing an exception handler, an exception can

preempt the exception handler if its priority is higher than the priority of the

exception being handled. When one exception preempts another, the

exceptions are called nested exceptions. See Exception entry on page 26

more information.

Return This occurs when the exception handler is completed, and:

● There is no pending exception with sufficient priority to be serviced

● The completed exception handler was not handling a late-arriving

exception.

The processor pops the stack and restores the processor state to the state it

had before the interrupt occurred. See Exception return on page 27 for more

information.

Tail-chaining This mechanism speeds up exception servicing. On completion of an

exception handler, if there is a pending exception that meets the

requirements for exception entry, the stack pop is skipped and control

transfers to the new exception handler.

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ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP