ST STM32F0 Series User Manual

PM0215 The STM32 Cortex-M0 processor
Doc ID 022979 Rev 1 19/91
2.2.1 Memory regions, types and attributes
The memory map is split into regions. Each region has a defined memory type, and some
regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
The memory types are:
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
Additional memory attributes include:
2.2.2 Memory system ordering of memory accesses
For most memory accesses caused by explicit memory access instructions, the memory
system does not guarantee that the order in which the accesses complete matches the
program order of the instructions, providing this does not affect the behavior of the
instruction sequence. Normally, if correct program execution depends on two memory
accesses completing in program order, software must insert a memory barrier instruction
between the memory access instructions, see Section 2.2.4: Software ordering of memory
accesses on page 20.
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs
before A2 in program order, the ordering of the memory accesses caused by two
instructions is:
Normal The processor can re-order transactions for efficiency, or
perform speculative reads.
Device The processor preserves transaction order relative to other
transactions to Device or Strongly-ordered memory.
Strongly-ordered The processor preserves transaction order relative to all other
transactions.
Execute Never (XN) Means the processor prevents instruction accesses. Any
attempt to fetch an instruction from an XN region causes a
HardFault exception.
Table 10. Ordering of memory accesses
(1)
1. - means that the memory system does not guarantee the ordering of the accesses.
< means that accesses are observed in program order, that is, A1 is always observed before A2.
A1
A2
Normal access
Device access Strongly
ordered
access
Non-shareable Shareable
Normal access - - - -
Device access, non-shareable - < - <
Device access, shareable - - < <
Strongly ordered access - < < <

ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history