ST STM32F0 Series User Manual

Core peripherals PM0215
78/91 Doc ID 022979 Rev 1
4.3.2 Interrupt control and state register (ICSR)
Address offset: 0x04
Reset value: 0x0000 0000
The ICSR:
● Provides:
– A set-pending bit for the Non-Maskable Interrupt (NMI) exception
– Set-pending and clear-pending bits for the PendSV and SysTick exceptions
● Indicates:
– The exception number of the exception being processed
– Whether there are preempted active exceptions
– The exception number of the highest priority pending exception
– Whether any interrupts are pending.
Caution: When you write to the ICSR, the effect is unpredictable if you:
● Write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
● Write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPE
NDSET
Reserved
PEND
SVSET
PEND
SVCLR
PEND
STSET
PENDS
TCLR
Reserved
ISRPE
NDING
Reserved
VECTPENDING[
5:4]
rw rw w rw w r r r
1514131211109876543210
VECTPENDING[3:0]
Reserved
VECTACTIVE[5:0]
r r r r rwrwrwrwrwrw
Bit 31 NMIPENDSET: NMI set-pending bit.
Write:
0: No effect
1: Change NMI exception state to pending.
Read:
0: NMI exception is not pending
1: NMI exception is pending
Because NMI is the highest-priority exception, normally the processor enter the NMI
exception handler as soon as it registers a write of 1 to this bit, and entering the handler clears
this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
Bits 30:29 Reserved
Bit 28 PENDSVSET: PendSV set-pending bit.
Write:
0: No effect
1: Change PendSV exception state to pending.
Read:
0: PendSV exception is not pending
1: PendSV exception is pending
Writing 1 to this bit is the only way to set the PendSV exception state to pending.

ST STM32F0 Series Specifications

General

Brand	ST
Model	STM32F0 Series
Category	Microcontrollers
Language	English