ST STM32F0 Series - Page 79

PM0215 Core peripherals
Doc ID 022979 Rev 1 79/91
Bit 27 PENDSVCLR: PendSV clear-pending bit. This bit is write-only. On a read, value is unknown.
0: No effect
1: Removes the pending state from the PendSV exception.
Bit 26 PENDSTSET: SysTick exception set-pending bit.
Write:
0: No effect
1: Change SysTick exception state to pending
Read:
0: SysTick exception is not pending
1: SysTick exception is pending
Bit 25 PENDSTCLR: SysTick exception clear-pending bit. Write-only. On a read, value is unknown.
0: No effect
1: Removes the pending state from the SysTick exception.
Bit 24:23 Reserved, must be kept cleared.
Bit 22 ISRPENDING: Interrupt pending flag, excluding NMI and Faults.
0: Interrupt not pending
1: Interrupt pending
Bits 21:18 Reserved, must be kept cleared.
Bits 17:12 VECTPENDING: Pending vector. Indicates the exception number of the highest priority
pending enabled exception.
0: No pending exceptions
Other values: The exception number of the highest priority pending enabled exception.
Bits 11:6 Reserved
Bits 5:0 VECTACTIVE Active vector. Contains the active exception number:
0: Thread mode
Other values: The exception number
(1)
of the currently active exception.
Note: Subtract 16 from this value to obtain CMSIS IRQ number required to index into the
Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers,
see Table 6 on page 14.
1. This is the same value as IPSR bits[5:0], see Interrupt program status register on page 14.