ST STM32F0 Series User Manual

PM0215 Core peripherals
Doc ID 022979 Rev 1 73/91
4.2.6 Interrupt priority register (IPR0-IPR7)
Address offset: 0x0300
Reset value: 0x0000 0000
The IPR registers provide an 8-bit priority field for each interrupt. These registers are only
word-accessible. Each register holds four priority fields, as shown in Figure 14.
Figure 14. IPR register mapping
See Interrupt set-enable register (ISER) on page 71 Accessing the Cortex-M0 NVIC
registers using CMSIS on page 70 for more information about the interrupt priority array, that
provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt N as follows:
● The corresponding IPR number, M, is given by M = N DIV 4
● The byte offset of the required Priority field in this register is N MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
Table 27. IPR bit assignments
Bits Name Function
[31:24] Priority, byte offset 3
Each priority field holds a priority value, 0-192. The lower the value,
the greater the priority of the corresponding interrupt. The processor
implements only bits[7:6] of each field, bits[5:0] read as zero and
ignore writes. This means writing 255 to a priority register saves
value 192 to the register.
[23:16] Priority, byte offset 2
[15:8] Priority, byte offset 1
[7:0] Priority, byte offset 0
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ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history