ST STM32F0 Series User Manual

Core peripherals PM0215
70/91 Doc ID 022979 Rev 1
4.2 Nested vectored interrupt controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it
uses. The NVIC supports:
● Up to 32 interrupts
● A programmable priority level of 0-192 in steps of 64 for each interrupt. A higher level
corresponds to a lower priority, so level 0 is the highest interrupt priority
● Level and pulse detection of interrupt signals
● Interrupt tail-chaining
● An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
4.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
CMSIS functions enable software portability between different Cortex-M profile processors.
To access the NVIC registers when using CMSIS, use the following functions:
Table 25. NVIC register summary
Address Name Type Reset value Description
0xE000E100 ISER RW 0x00000000 Table 4.2.2: Interrupt set-enable register (ISER) on page 71
0XE000E180 ICER RW 0x00000000 Table 4.2.3: Interrupt clear-enable register (ICER) on page 71
0XE000E200 ISPR RW 0x00000000 Table 4.2.4: Interrupt set-pending register (ISPR) on page 72
0XE000E280 ICPR RW 0x00000000
Table 4.2.5: Interrupt clear-pending register (ICPR) on
page 72
0xE000E400-
0xE000E41C
IPR0-IPR7 RW 0x00000000 Table 4.2.6: Interrupt priority register (IPR0-IPR7) on page 73
Table 26. CMSIS access NVIC functions
CMSIS function
(1)
Description
void NVIC_EnableIRQ(IRQn_Type IRQn) Enables an interrupt or exception.
void NVIC_DisableIRQ(IRQn_Type IRQn) Disables an interrupt or exception.
void NVIC_SetPendingIRQ(IRQn_Type IRQn) Sets pending status of interrupt or exception to 1.
void NVIC_ClearPendingIRQ(IRQn_Type IRQn) Clears pending status of interrupt / exception to 0.
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Reads the pending status of interrupt / exception.
Returns non-zero value if pending status is set to 1.
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Sets priority of an interrupt / exception with configurable
priority level to 1.
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Reads priority of an interrupt or exception with
configurable priority level.
Returns the current priority level.
1. The input parameter IRQn is the IRQ number,

ST STM32F0 Series Specifications

General

Series	STM32F0
Core	ARM Cortex-M0
Operating Frequency	Up to 48 MHz
Flash Memory	16 KB to 256 KB
SRAM	4 KB to 32 KB
ADC Resolution	12-bit
ADC Channels	Up to 16
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit (some series)
Communication Interfaces	I2C, SPI, USART, USB, CAN
Operating Temperature	-40°C to 85°C
Package Options	LQFP, TSSOP, UFQFPN, WLCSP

Summary

Introduction to STM32F0xxx Programming

About this document

1.1 Typographical conventions

Defines typographical conventions used in the document.

1.2 List of abbreviations for registers

Lists abbreviations used for register descriptions.

1.3 About the STM32 Cortex-M0 processor and core peripherals

Overview of the Cortex-M0 processor and its core peripherals.

The STM32 Cortex-M0 processor

2.1 Programmers model

Describes the Cortex-M0 programmer's model, modes, and stacks.

2.2 Memory model

Details the processor memory map and memory access behavior.

2.3 Exception model

Explains the exception model, states, types, and priorities.

2.4 Fault handling

Covers fault handling mechanisms, including lockup states.

2.5 Power management

Describes sleep and deep sleep modes for power saving.

The STM32 Cortex-M0 instruction set

3.1 Instruction set summary

Summarizes the Thumb instruction set supported by the Cortex-M0.

3.4 Memory access instructions

Covers instructions for loading and storing data from/to memory.

3.5 General data processing instructions

Describes instructions for arithmetic, logical, and data manipulation operations.

3.6 Branch and control instructions

Details instructions for program flow control and branching.

Core peripherals

4.1 About the STM32 Cortex-M0 core peripherals

Introduces the core peripherals and their address map.

4.2 Nested vectored interrupt controller (NVIC)

Details the NVIC's support for interrupts and its registers.

4.3 System control block (SCB)

Describes the SCB for system implementation information and control.

4.4 SysTick timer (STK)

Explains the SysTick timer's functionality and registers.

Revision history