PM0215 The STM32 Cortex-M0 instruction set
Doc ID 022979 Rev 1 41/91
3.4 Memory access instructions
Tabl e 18 shows the memory access instructions:
Table 18. Memory access instructions
Mnemonic Brief description See
ADR Load PC-relative address ADR on page 42
LDM Load multiple registers LDM and STM on page 46
LDR{type} Load register using immediate offset LDR and STR, immediate offset on page 43
LDR{type} Load register using register offset LDR and STR, register offset on page 44
LDR Load register using PC-relative address LDR, PC-relative on page 45
LDRD Load register dual LDR and STR, immediate offset on page 43
POP Pop registers from stack PUSH and POP on page 47
PUSH Push registers onto stack PUSH and POP on page 47
STM Store multiple registers LDM and STM on page 46
STR{type} Store register using immediate offset LDR and STR, immediate offset on page 43
STR{type} Store register using register offset LDR and STR, register offset on page 44