Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 287
UG196 (v1.3) May 25, 2007
DRP Address by Attribute
R
CLK_COR_SEQ_2_1_1
1b<3> 1b<2> 1b<1> 1b<0>
1a<15> 1a<14> 1a<13> 1a<12>
1a<11>
1a<10>
CLK_COR_SEQ_2_2_0
34<2> 34<3> 34<4> 34<5> 34<6> 34<7> 34<8> 34<9>
34<10>
34<11>
CLK_COR_SEQ_2_2_1
1b<13> 1b<12>
1b<11>
1b<10>
1b<9> 1b<8> 1b<7> 1b<6> 1b<5> 1b<4>
CLK_COR_SEQ_2_3_0
33<8> 33<9>
33<10>
33<11>
33<12> 33<13> 33<14> 33<15>
34<0> 34<1>
CLK_COR_SEQ_2_3_1
1c<7> 1c<6> 1c<5> 1c<4> 1c<3> 1c<2> 1c<1> 1c<0>
1b<15> 1b<14>
CLK_COR_SEQ_2_4_0
32<14> 32<15>
33<0> 33<1> 33<2> 33<3> 33<4> 33<5> 33<6> 33<7>
CLK_COR_SEQ_2_4_1
1d<1> 1d<0>
1c<15> 1c<14> 1c<13> 1c<12>
1c<11>
1c<10>
1c<9> 1c<8>
CLK_COR_SEQ_2_ENABLE_0
32<10>
32<11>
32<12> 32<13>
CLK_COR_SEQ_2_ENABLE_1
1d<5> 1d<4> 1d<3> 1d<2>
CLK_COR_SEQ_2_USE_0
32<9>
CLK_COR_SEQ_2_USE_1
1d<6>
CLK_CORRECT_USE_0
38<7>
Ta ble D - 2 : DRP Address by Attribute (Continued)
Attribute
Bit
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English