Xilinx Virtex-5 RocketIO GTP User Manual

288 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
CLK_CORRECT_USE_1
17<8>
CLK25_DIVIDER
26<11>
26<10>
26<9>
CLKINDC_B
4<3>
CLKNORTH_SEL
4<8>
CLKSOUTH_SEL
4<7>
COM_BURST_VAL_0
32<5> 32<6> 32<7> 32<8>
COM_BURST_VAL_1
1d<10>
1d<9> 1d<8> 1d<7>
COMMA_10B_ENABLE_0
31<11>
31<12> 31<13> 31<14> 31<15>
32<0> 32<1> 32<2> 32<3> 32<4>
COMMA_10B_ENABLE_1
1e<4> 1e<3> 1e<2> 1e<1> 1e<0>
1d<15> 1d<14> 1d<13> 1d<12>
1d<11>
COMMA_DOUBLE_0
31<10>
COMMA_DOUBLE_1
1e<5>
DEC_MCOMMA_DETECT_0
31<9>
DEC_MCOMMA_DETECT_1
1f<3>
Table D-2: DRP Address by Attribute (Continued)
Attribute
Bit
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English