Xilinx Virtex-5 RocketIO GTP

304 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
7
CHAN_
BOND_SEQ_2
_2_0[3]
DEC_VALID_
COMMA_
ONLY_0
COM_BURST
_VAL_0[2]
CLK_COR_
SEQ_2_4_0[9]
CLK_COR_
SEQ_2_2_0[5]
CLK_COR_
SEQ_1_
ENABLE_
0[2]
CLK_COR_
SEQ_1_3_0[3]
CLK_COR_
SEQ_1_2_0[9]
8
CHAN_
BOND_SEQ_2
_2_0[2]
DEC_
PCOMMA_
DETECT_0
COM_BURST
_VAL_0[3]
CLK_COR_
SEQ_2_3_0[0]
CLK_COR_
SEQ_2_2_0[6]
CLK_COR_
SEQ_1_
ENABLE_0[3]
CLK_COR_
SEQ_1_3_0[4]
CLK_COR_
SEQ_1_1_0[0]
9
CHAN_
BOND_SEQ_2
_2_0[1]
DEC_
MCOMMA_
DETECT_0
CLK_COR_
SEQ_2_USE_0
CLK_COR_
SEQ_2_3_0[1]
CLK_COR_
SEQ_2_2_0[7]
CLK_COR_
SEQ_1_
ENABLE_0[4]
CLK_COR_
SEQ_1_3_0[5]
CLK_COR_
SEQ_1_1_0[1]
10
CHAN_
BOND_SEQ_2
_2_0[0]
COMMA_
DOUBLE_0
CLK_COR_
SEQ_2_
ENABLE_0[1]
CLK_COR_
SEQ_2_3_0[2]
CLK_COR_
SEQ_2_2_0[8]
CLK_COR_
SEQ_1_4_0[0]
CLK_COR_
SEQ_1_3_0[6]
CLK_COR_
SEQ_1_1_0[2]
11
CHAN_
BOND_SEQ_2
_3_0[9]
COMMA_
10B_ENABLE
_0[0]
CLK_COR_
SEQ_2_
ENABLE_0[2]
CLK_COR_
SEQ_2_3_0[3]
CLK_COR_
SEQ_2_2_0[9]
CLK_COR_
SEQ_1_4_0[1]
CLK_COR_
SEQ_1_3_0[7]
CLK_COR_
SEQ_1_1_0[3]
12
MCOMMA_
DETECT_0
COMMA_
10B_ENABLE
_0[1]
CLK_COR_
SEQ_2_
ENABLE_0[3]
CLK_COR_
SEQ_2_3_0[4]
CLK_COR_
SEQ_2_1_0[0]
CLK_COR_
SEQ_1_4_0[2]
CLK_COR_
SEQ_1_3_0[8]
CLK_COR_
SEQ_1_1_0[4]
13
MCOMMA_
10B_VALUE_
0[0]
COMMA_
10B_ENABLE
_0[2]
CLK_COR_
SEQ_2_
ENABLE_0[4]
CLK_COR_
SEQ_2_3_0[5]
CLK_COR_
SEQ_2_1_0[1]
CLK_COR_
SEQ_1_4_0[3]
CLK_COR_
SEQ_1_3_0[9]
CLK_COR_
SEQ_1_1_0[5]
14
MCOMMA_
10B_VALUE_
0[1]
COMMA_
10B_ENABLE
_0[3]
CLK_COR_
SEQ_2_4_0[0]
CLK_COR_
SEQ_2_3_0[6]
CLK_COR_
SEQ_2_1_0[2]
CLK_COR_
SEQ_1_4_0[4]
CLK_COR_
SEQ_1_2_0[0]
CLK_COR_
SEQ_1_1_0[6]
15
MCOMMA_
10B_VALUE_
0[2]
COMMA_
10B_ENABLE
_0[4]
CLK_COR_
SEQ_2_4_0[1]
CLK_COR_
SEQ_2_3_0[7]
CLK_COR_
SEQ_2_1_0[3]
CLK_COR_
SEQ_1_4_0[5]
CLK_COR_
SEQ_1_2_0[1]
CLK_COR_
SEQ_1_1_0[7]
Table D-9: DRP Addresses 30 through 37 (Continued)
Bit
Address
30 31 32 33 34 35 36 37
Table D-10: DRP Addresses 38 through 3F
Bit
Address
38 39 3A 3B 3C 3D 3E 3F
0
CLK_COR_
SEQ_1_1_0[8]
CLK_COR_
MAX_LAT_
0[1]
CHAN_
BOND_SEQ_2
_ENABLE_
0[3]
Do Not
Modify
TRANS_
TIME_TO_P2
_0[3]
TRANS_
TIME_NON_
P2_0[3]
TRANS_
TIME_FROM
_P2_0[3]
SATA_MIN_
WAKE_0[2]
1
CLK_COR_
SEQ_1_1_0[9]
CLK_COR_
MAX_LAT_
0[2]
CHAN_
BOND_SEQ_2
_ENABLE_
0[4]
Do Not
Modify
TRANS_
TIME_TO_P2
_0[4]
TRANS_
TIME_NON_
P2_0[4]
TRANS_
TIME_FROM
_P2_0[4]
SATA_MIN_
WAKE_0[3]
2
CLK_COR_
REPEAT_WAIT
_0[0]
CLK_COR_
MAX_LAT_
0[3]
Do Not
Modify
Do Not
Modify
TRANS_
TIME_TO_P2
_0[5]
TRANS_
TIME_NON_
P2_0[5]
TRANS_
TIME_FROM
_P2_0[5]
SATA_MIN_
WAKE_0[4]
3
CLK_COR_
REPEAT_WAIT
_0[1]
CLK_COR_
MAX_LAT_
0[4]
OOBDETECT_
THRESHOLD
_0[0]
Do Not
Modify
TRANS_
TIME_TO_P2
_0[6]
TRANS_
TIME_NON_
P2_0[6]
TRANS_
TIME_FROM
_P2_0[6]
SATA_MIN_
WAKE_0[5]