Xilinx Virtex-5 RocketIO GTP

306 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
Table D-11: DRP Addresses 40 through 47
Bit
Address
40 41 42 43 44 45 46 47
0
SATA_MAX_
WAKE_0[0]
SATA_MAX_
BURST_0[4]
RX_LOS_
INVALID_
INCR_0[1]
PRBS_ERR_
THRESHOLD
_0[12]
PRBS_ERR_
THRESHOLD
_0[28]
PMA_CDR_
SCAN_0[12]
PLL_
TXDIVSEL_
OUT_0[1]
Do Not
Modify
1
SATA_MAX_
WAKE_0[1]
SATA_MAX_
BURST_0[5]
RX_LOS_
INVALID_
INCR_0[2]
PRBS_ERR_
THRESHOLD
_0[13]
PRBS_ERR_
THRESHOLD
_0[29]
PMA_CDR_
SCAN_0[13]
PLL_SATA_0
CHAN_
BOND_SEQ_2
_3_0[8]
2
SATA_MAX_
WAKE_0[2]
SATA_IDLE_
VAL_0[0]
RX_DECODE
_SEQ_
MATCH_0
PRBS_ERR_
THRESHOLD
_0[14]
PRBS_ERR_
THRESHOLD
_0[30]
PMA_CDR_
SCAN_0[14]
PLL_
RXDIVSEL_
OUT_0[0]
CHAN_
BOND_SEQ_2
_3_0[7]
3
SATA_MAX_
WAKE_0[3]
SATA_IDLE_
VAL_0[1]
RX_BUFFER_
USE_0
PRBS_ERR_
THRESHOLD
_0[15]
PRBS_ERR_
THRESHOLD
_0[31]
PMA_CDR_
SCAN_0[15]
PLL_
RXDIVSEL_
OUT_0[1]
CHAN_
BOND_SEQ_2
_3_0[6]
4
SATA_MAX_
WAKE_0[4]
SATA_IDLE_
VAL_0[2]
PRBS_ERR_
THRESHOLD
_0[0]
PRBS_ERR_
THRESHOLD
_0[16]
PMA_CDR_
SCAN_0[0]
PMA_CDR_
SCAN_0[16]
PCOMMA_
DETECT_0
CHAN_
BOND_SEQ_2
_3_0[5]
5
SATA_MAX_
WAKE_0[5]
SATA_BURST
_VAL_0[0]
PRBS_ERR_
THRESHOLD
_0[1]
PRBS_ERR_
THRESHOLD
_0[17]
PMA_CDR_
SCAN_0[1]
PMA_CDR_
SCAN_0[17]
PCOMMA_
10B_VALUE_
0[0]
CHAN_
BOND_SEQ_2
_3_0[4]
6
SATA_MAX_
INIT_0[0]
SATA_BURST
_VAL_0[1]
PRBS_ERR_
THRESHOLD
_0[2]
PRBS_ERR_
THRESHOLD
_0[18]
PMA_CDR_
SCAN_0[2]
PMA_CDR_
SCAN_0[18]
PCOMMA_
10B_VALUE_
0[1]
CHAN_
BOND_SEQ_2
_3_0[3]
7
SATA_MAX_
INIT_0[1]
SATA_BURST
_VAL_0[2]
PRBS_ERR_
THRESHOLD
_0[3]
PRBS_ERR_
THRESHOLD
_0[19]
PMA_CDR_
SCAN_0[3]
PMA_CDR_
SCAN_0[19]
PCOMMA_
10B_VALUE_
0[2]
CHAN_
BOND_SEQ_2
_3_0[2]
8
SATA_MAX_
INIT_0[2]
RX_XCLK_
SEL_0
PRBS_ERR_
THRESHOLD
_0[4]
PRBS_ERR_
THRESHOLD
_0[20]
PMA_CDR_
SCAN_0[4]
PMA_CDR_
SCAN_0[20]
PCOMMA_
10B_VALUE_
0[3]
CHAN_
BOND_SEQ_2
_3_0[1]
9
SATA_MAX_
INIT_0[3]
RX_STATUS_
FMT_0
PRBS_ERR_
THRESHOLD
_0[5]
PRBS_ERR_
THRESHOLD
_0[21]
PMA_CDR_
SCAN_0[5]
PMA_CDR_
SCAN_0[21]
PCOMMA_
10B_VALUE_
0[4]
CHAN_
BOND_SEQ_2
_3_0[0]
10
SATA_MAX_
INIT_0[4]
RX_SLIDE_
MODE_0
PRBS_ERR_
THRESHOLD
_0[6]
PRBS_ERR_
THRESHOLD
_0[22]
PMA_CDR_
SCAN_0[6]
PMA_CDR_
SCAN_0[22]
PCOMMA_
10B_VALUE_
0[5]
CHAN_
BOND_SEQ_2
_4_0[9]
11
SATA_MAX_
INIT_0[5]
RX_LOS_
THRESHOLD
_0[0]
PRBS_ERR_
THRESHOLD
_0[7]
PRBS_ERR_
THRESHOLD
_0[23]
PMA_CDR_
SCAN_0[7]
PMA_CDR_
SCAN_0[23]
PCOMMA_
10B_VALUE_
0[6]
CHAN_
BOND_SEQ_2
_4_0[8]
12
SATA_MAX_
BURST_0[0]
RX_LOS_
THRESHOLD
_0[1]
PRBS_ERR_
THRESHOLD
_0[8]
PRBS_ERR_
THRESHOLD
_0[24]
PMA_CDR_
SCAN_0[8]
PMA_CDR_
SCAN_0[24]
PCOMMA_
10B_VALUE_
0[7]
CHAN_
BOND_SEQ_2
_4_0[7]
13
SATA_MAX_
BURST_0[1]
RX_LOS_
THRESHOLD
_0[2]
PRBS_ERR_
THRESHOLD
_0[9]
PRBS_ERR_
THRESHOLD
_0[25]
PMA_CDR_
SCAN_0[9]
PMA_CDR_
SCAN_0[25]
PCOMMA_
10B_VALUE_
0[8]
CHAN_
BOND_SEQ_2
_4_0[6]
14
SATA_MAX_
BURST_0[2]
RX_LOSS_OF
_SYNC_FSM_
0
PRBS_ERR_
THRESHOLD
_0[10]
PRBS_ERR_
THRESHOLD
_0[26]
PMA_CDR_
SCAN_0[10]
PMA_CDR_
SCAN_0[26]
PCOMMA_
10B_VALUE_
0[9]
CHAN_
BOND_SEQ_2
_4_0[5]
15
SATA_MAX_
BURST_0[3]
RX_LOS_
INVALID_
INCR_0[0]
PRBS_ERR_
THRESHOLD
_0[11]
PRBS_ERR_
THRESHOLD
_0[27]
PMA_CDR_
SCAN_0[11]
PLL_
TXDIVSEL_
OUT_0[0]
PCI_EXPRESS
_MODE_0
CHAN_
BOND_SEQ_2
_4_0[4]