Xilinx Virtex-5 RocketIO GTP

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 69
UG196 (v1.3) May 25, 2007
Clocking
R
Figure 5-3: GTP Transceiver Clocking
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
MGTREFCLKP
MGTREFCLKN
MGTREFCLKP
MGTREFCLKN
MGTREFCLKP
MGTREFCLKN
MGTREFCLKP
MGTREFCLKN
MGTREFCLKP
MGTREFCLKN
MGTREFCLKP
MGTREFCLKN
MGTREFCLKP
MGTREFCLKN
MGTREFCLKP
MGTREFCLKN
GREFCLK
GREFCLK
GREFCLK
GREFCLK
GREFCLK
GREFCLK
GREFCLK
GREFCLK
Clock
Muxing
Clock
Muxing
Clock
Muxing
Clock
Muxing
Clock
Muxing
Clock
Muxing
Clock
Muxing
Clock
Muxing
GTP
Dedicated
Clock
Routing
GTP
Dedicated
Clock
Routing
GTP
Dedicated
Clock
Routing
GTP
Dedicated
Clock
Routing
GTP
Dedicated
Clock
Routing
GTP
Dedicated
Clock
Routing
GTP
Dedicated
Clock
Routing
GTP
Dedicated
Clock
Routing
UG196_c5_03_110206
IBUFDS
IBUFDS
IBUFDS
IBUFDS
IBUFDS
IBUFDS
IBUFDS
IBUFDS
BUFG/
BUFR
BUFG/
BUFR
BUFG/
BUFR
BUFG/
BUFR
BUFG/
BUFR
BUFG/
BUFR
BUFG/
BUFR
BUFG/
BUFR
Note: Refer to Chapter 10, “GTP-to-Board Interface” REFCLK Guidelines for IBUFDS details.