Xilinx Virtex-5 RocketIO GTP

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 97
UG196 (v1.3) May 25, 2007
FPGA TX Interface
R
Figure 6-8: REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface
GTP
Transceiver
GTP_DUAL
Tile
GTP
Transceiver
UG196_c6_08_040907
PLL_BASE
CLKIN
RST
CLKOUT0
REFCLKOUT
PLLLKDET
TXUSRCLK2
TXUSRCLK
TXUSRCLK2
TXUSRCLK
TXDATA (16 or 20 bits)
CLKOUT1
LOCKED
TXDATA (16 or 20 bits)
Design in
FPGA
BUFG