Name: Xilinx Virtex-5 RocketIO GTP
Brand: Xilinx
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Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 97

UG196 (v1.3) May 25, 2007

FPGA TX Interface

Figure 6-8: REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface

GTP

Transceiver

GTP_DUAL

Tile

GTP

Transceiver

UG196_c6_08_040907

PLL_BASE

CLKIN

RST

CLKOUT0

REFCLKOUT

PLLLKDET

TXUSRCLK2

TXUSRCLK

TXUSRCLK2

TXUSRCLK

TXDATA (16 or 20 bits)

CLKOUT1

LOCKED

TXDATA (16 or 20 bits)

Design in

FPGA

BUFG

Default Chapter2
- Default Chapter2
  - Revision History2
  - Table of Contents5
- Preface: about this Guide13
Section 1: FPGA Level Design17
Section 2: Board Level Design221
Section 3: Appendices255

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Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English

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Xilinx Virtex-5 RocketIO GTP User Manual

Table of Contents

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Xilinx Virtex-5 RocketIO GTP Specifications

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