74 Chapter 2
Block Diagrams
A12 Analog IF Assembly
21.4 MHz Anti-Alias Filter
This filter serves two purposes. First, it rejects the image band at
31.4 MHz to 41.4 MHz. Second, it band limits the signal to a width of
10 MHz, and so provides much of the anti-alias filtering for the ADC.
Mixer
The third mixer converts the incoming 21.4 MHz second IF down to the
final third IF at 7.5 MHz. This is accomplished by mixing the 21.4 MHz
second IF with a 28.9 MHz third LO. The difference frequency is
7.5 MHz
Third L.O.
The 28.9 MHz third LO signal is phase locked to the 10 MHz frequency
reference from the A18 reference assembly.
Post Down Conversion Filtering
There are two post-mixing filters for the 7.5 MHz final IF. The
12.5 MHz low pass filter removes high order mixing products from the
third LO, as well as the 21.4 MHz feed-through. The 2 MHz wide band
pass filter provides additional filtering for narrow resolution
bandwidths, and is used to improve dynamic-range, free of spurious
signals.
Calibrator and Sample Rate Oscillators
A host of complex signals are used during the vector calibration. This
output is fed to the A17 RF assembly. The vector calibration is
performed at instrument power up, and a background calibration will
be performed if the auto cal feature is activated (press
System,
Alignments, Auto Align, and toggle the Auto Align key to On, to activate
the auto cal feature).
Clock Generator
The clock is a 30MSa/s differential ECL clock that is distributed on the
motherboard to the digital IF as SR_L and SR_H (Sample Rate low and
high). The clock generator is locked to the 10 MHz reference signal.
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