EasyManuals Logo
Home>Agilent Technologies>Test Equipment>E4406A VSA Series

Agilent Technologies E4406A VSA Series Service Guide

Agilent Technologies E4406A VSA Series
266 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #32 background imageLoading...
Page #32 background image
32 Chapter 1
Troubleshooting
Auto-Align Tests
Auto-Align Tests
The following tests are part of the auto-alignment procedure that occurs
at instrument power-up. All alignment procedures have one of three
outcomes:
SUCCESS data is propagated to the alignment database
FAILURE no data stored, and an ERROR is propagated until
future success
ABORT no data stored, and no ERROR messages
The data collected during the auto-align procedure, called the “cal
database”, is stored in DRAM by the CPU.
All alignments are accessible via SCPI, and the query form of
alignment requests returns ZERO for SUCCESS, non-ZERO for FAILURE
or ABORT. All alignments can be aborted at any time by using the
ESCAPE key.
Table 1-3 Sequence for Auto-Align Procedures
Procedure Name Procedure Description
Diagnostic Check As a precursor to any alignment (or full alignment), this procedure runs a quick diagnostic
check to see if the system is even capable of completing the alignment. It checks for the
possible presence of incoming RF energy at 50 MHz to be less than approximately 0 dBm.
RF input power levels greater than 0 dB could leak through the calibrator switch and add
energy to the calibrator signal. It also checks for unlock condition of the 28.9 MHz and 30
MHz oscillators on the A12 analog IF assembly.
Trigger Interpolator The trigger interpolator provides a way to measure trigger timing to a fine precision. A
unique trigger is used, which has timing that can be varied relative to the sample clock
using an 8-bit control dac on the A12 analog IF. If it is not monotonic, or the expected
variation is not verified, this alignment will FAIL.
ADC Offset DACs Offset dacs for each of the 6 ADC range positions on the A10 digital IF assembly are aligned
to reduce the overall DC offset.
ADC Dither CF The ADC dither needs to be centered to prevent its own harmonics from folding back into
the center of the IF passband. This routine adjusts the dither dac on the A10 digital IF.
ADC RAM Gains Each of the 6 ADC range positions has its own page of RAM memory. This is a mapping of
ADC bits to “output” Data bits. This RAM memory is on the A10 digital IF assembly.
This alignment uses the 50 MHz CW signal, from the A17 RF assembly, to measure the
response of each range page. The RF input attenuator and analog IF main gain dac are
dynamically adjusted to help keep the actual ADC signal level approximately the same.
Relative measurements between each page transition ensure correctness even when moving
main gain or attenuator around. Gain values for each page are stored away into the Cal
database, and the RAM pages are then re-written.
IF Image Filter The 321 MHz cal osc, on the A17 RF assembly, is used to align the 8 dacs of the image filter
on the A12 analog IF assembly.
IF Gain Curve The A12 analog IF assembly has a gain control dac that is called the “Main Gain”. It is used
to compensate for analog IF Prefilter BW gain variations, so that the gain of the entire IF
path (before ADC) remains approximately constant. It is the only gain stage that gets
varied during normal instrument operation. This alignment generates the curve coefficients
which characterize the gain vs dac number associated with this stage.

Table of Contents

Other manuals for Agilent Technologies E4406A VSA Series

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Agilent Technologies E4406A VSA Series and is the answer not in the manual?

Agilent Technologies E4406A VSA Series Specifications

General IconGeneral
BrandAgilent Technologies
ModelE4406A VSA Series
CategoryTest Equipment
LanguageEnglish

Related product manuals