12 16-BIT PWM TIMER (T16E)
S1C17624/604/622/602/621 TECHNICAL MANUAL
Seiko Epson Corporation
12-9
D2 OUTEN: Clock Output Enable Bit
Controls the TOUTx and TOUTNx signal (timer output clock) outputs.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Writing 1 to OUTEN outputs the TOUTx and TOUTNx signals from the corresponding output pins.
Writing 0 to OUTEN stops the output, and the output pins go to the off level according to the INVOUT
and INITOL settings. The TOUTx/TOUTNx port function must be selected using the port function
se-
lect register before outputting the TOUTx and TOUTNx signals.
D1 T16ERST: Timer Reset Bit
Resets the counter.
1 (W): Reset
0 (W): Ignored
0 (R): Always 0 when being read (default)
Writing 1 to T16ERST resets the counter.
D0 T16ERUN: Timer Run/Stop Control Bit
Controls the timer Run/Stop.
1 (R/W): Run
0 (R/W): Stop (default)
T16E starts counting when 1 is written to T16ERUN and stops when 0 is written. The counter data is
retained when stopped until the subs
equent reset or run. Counting can be resumed when switched from
stop to run from the data retained.
T16E Ch.x Clock Division Ratio Select Register (T16E_DFx)
Register name Address Bit Name Function Setting Init. R/W Remarks
T16E Ch.x
Clock
Division Ratio
Select Register
(T16E_DFx)
0x5308
(16 bits)
D15–4
–
reserved – – – 0 when being read.
D3–0
T16EDF[3:0]
Clock division ratio select T16EDF[3:0] Division ratio 0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D[15:4] Reserved
D[3:0] T16EDF[3:0]: Clock Division Ratio Select Bits
Selects a PCLK division ratio to generate the count clock.
9.2 PCLK Division Ratio SelectionTable 12.
T16EDF[3:0] Division ratio T16EDF[3:0] Division ratio
0xf Reserved 0x7 1/128
0xe 1/16384 0x6 1/64
0xd 1/8192 0x5 1/32
0xc 1/4096 0x4 1/16
0xb 1/2048 0x3 1/8
0xa 1/1024 0x2 1/4
0x9 1/512 0x1 1/2
0x8 1/256 0x0 1/1
(Default: 0x0)
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