Epson S1C17624 - RTC Interrupt Status Register (RTC_INTSTAT); RTC Interrupt Mode Register (RTC_INTMODE)

8 REAL-TIME CLOCK (RTC)
8-10
Seiko Epson Corporation S1C17624/604/622/602/621 TECHNICAL MANUAL
RTC Interrupt Status Register (RTC_INTSTAT)
Register name Address Bit Name Function Setting Init. R/W Remarks
RTC Interrupt
Status Register
(RTC_INTSTAT)
0x5140
(8 bits)
D7–1
–
reserved – – – 0 when being read.
D0
RTCIRQ
Interrupt status 1 Occurred 0
Not occurred X (0) R/W Reset by writing 1.
Init.: ( ) indicates the value set after a software reset (RTCRST → 1 → 0) is performed.
D[7:1] Reserved
D0 RTCIRQ: Interrupt Status Bit
This bit indicates whether a cause of RTC interrupt occurred as follows:
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred (software reset value)
1 (W): Resets this bit to
0
0 (W): Has no effect
This bit is set at cyclic interrupt intervals set up by RTCT[2:0]/RTC_INTMODE register. When RTC
interrupts have been enabled by RTCIEN/RTC_INTMODE register at this time, an interrupt request is
sent to the ITC.
Note: Writing 1 to this status bit clears it. Because this bit is not cleared in hardware, be sure to clear
it in software after an interrupt is generated. If this bit remains set while interrupts are re-en-
abled or control is returned from the interrupt handler routine by the reti instruction, the same
interrupt may be generated again. Moreover, the value of this bit is indeterminate after power-
on, and is not initialized to 0 by initial reset. To prevent the occurrence of unwanted RTC inter-
rupts, be sure to reset this bit in software after power-on and initial reset.
RTC Interrupt Mode Register (RTC_INTMODE)
Register name Address Bit Name Function Setting Init. R/W Remarks
RTC Interrupt
Mode Register
(RTC_INTMODE)
0x5141
(8 bits)
D7–5
–
reserved – – – 0 when being read.
D4–2
RTCT[2:0]
RTC interrupt cycle setup RTCT[2:0]
Cycle X
(0x1)
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/128 second
1/256 second
1/512 second
1 hour
1 minute
1 second
1/64 second
D1
RTCIMD
RTC interrupt mode select 1 Level sense 0
Edge trigger X (1) R/W
D0
RTCIEN
RTC interrupt enable 1 Enable 0 Disable X (0) R/W
Init.: ( ) indicates the value set after a software reset (RTCRST → 1 → 0) is performed.
D[7:5] Reserved
D[4:2] RTCT[2:0]: RTC Interrupt Cycle Setup Bits
Th
ese bits select the RTC interrupt cycle.
5.2 Interrupt Cycle SettingsTable 8.
RTCT[2:0] Interrupt cycle
0x7 Reserved
0x6 1/128 second
0x5 1/256 second
0x4 1/512 second
0x3 1 hour
0x2 1 minute
0x1 1 second
0x0 1/64 second
(Default: indeterminate, software reset: 0x1)
RTCIRQ/RTC_INTSTAT register is set by a count-up pulse of the interrupt cycle counter selected.
When RTC interrupts are enabled by RTCIEN, an interrupt request is sent to the ITC.
RTCT[2:0] should be set while RTC interrupts are
disabled. (These bits may also be set simultaneously
when RTC interrupts are enabled.)