APPENDIX A LIST OF I/O REGISTERS
AP-A-26
Seiko Epson Corporation
S1C17624/604/622/602/621 TECHNICAL MANUAL
Register name Address Bit Name Function Setting Init. R/W Remarks
RFC
Interrupt
Mask
Register
(RFC_IMSK)
0x53ac
(16 bits)
D15–5
–
reserved – – – 0 when being read.
D4
OVTCIE
TC overflow error
interrupt enable 1 Enable 0 Disable 0 R/W
D3
OVMCIE
MC overflow error
interrupt enable 1 Enable 0 Disable 0 R/W
D2
ESENBIE
Sensor B oscillation completion
interrupt enable
1 Enable 0 Disable 0 R/W
D1
ESENAIE
Sensor A oscillation completion
interrupt enable
1 Enable 0 Disable 0 R/W
D0
EREFIE
Reference oscillation completion
interrupt enable
1 Enable 0 Disable 0 R/W
RFC Interrupt
Flag Register
(RFC_IFLG)
0x53ae
(16 bits)
D15–5
–
reserved – – – 0 when being read.
D4
OVTCIF
TC overflow error
interrupt flag 1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0 R/W Reset by writing 1.
D3
OVMCIF
MC overflow error
interrupt flag 0 R/W
D2
ESENBIF
Sensor B oscillation completion
interrupt flag
0 R/W
D1
ESENAIF
Sensor A oscillation completion
interrupt flag
0 R/W
D0
EREFIF
Reference oscillation completion
interrupt flag
0 R/W
0x5068, 0x5400–0x540c 16-bit PWM Timer (T16A2) Ch.0 (S1C17624/604)
Register name Address Bit Name Function Setting Init. R/W Remarks
T16A Clock
Control Register
Ch.0
(T16A_CLK0)
0x5068
(8 bits)
D7–4
CLKDIV
[3:0]
Clock division ratio select
CLKDIV[3:0]
Division ratio 0x0 R/W
OSC3 or
IOSC
OSC1
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
–
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
–
–
–
–
–
–
–
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D3–2
CLKSRC
[1:0]
Clock source select CLKSRC[1:0] Clock source 0x0 R/W
0x3
0x2
0x1
0x0
External clock
OSC3
OSC1
IOSC
D1
MULTIMD
Multi-comparator/capture mode
select
1 Multi 0 Normal 0 R
/W
D0
CLKEN
Count clock enable 1 Enable 0 Disable 0 R/W
T16A
Counter
Ch.0
Control
Register
(T16A_CTL0)
0x5400
(16 bits)
D15–7
–
reserved – – – 0 when being read.
D6
HCM
Half clock mode enable 1 Enable 0 Disable 0 R/W
D5–4
CCABCNT
[1:0]
Counter select CCABCNT[1:0] Counter Ch. 0x0 R/W
0x3, 0x2
0x1
0x0
reserved
Ch.1
Ch.0
D3
CBUFEN
Compare buffer enable 1 Enable 0 Disable 0 R/W
D2
TRMD
Count mode select 1 One-shot 0 Repeat 0 R/W
D1
PRESET
Counter reset 1 Reset 0 Ignored 0 W 0 when being read.
D0
PRUN
Counter run/stop control 1 Run 0 Stop 0 R/W
T16A Counter
Ch.0 Data
Register
(T16A_TC0)
0x5402
(16 bits)
D15–0
T16ATC
[15:0]
Counter data
T16ATC15 = MSB
T16ATC0 = LSB
0x0 to 0xffff 0x0 R
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